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�� �� 8 M� ( F� M� qcom,kaanapali qcom,kaanapali board-id # ,default_process-kaanapali-1.0-adsp 6 � soc @ � glink qcom,glink P H proc-info X xport-smem-config edge-01 ] i @ s | � N edge-02 ] i @ s | � N edge-03 ] i s | 9 � N edge-04 ] i @ s | � N xport-qmp-config edge-01 �aop_adsp ] � � � | � � ipc_router qcom,ipc_router proc-info adsp devcfg-glink-xals edge-01 SMEM apss #IPCRTR + 3� < G � � � edge-02 SMEM mpss #IPCRTR + 3� < G � � � edge-03 SMEM cdsp #IPCRTR + 3� < G � � � devcfg-mhi-xals edge-01 MHI wpss O 2 Z 3 smp2p qcom,smp2p proc-info e m t smp2p-interrupts intr-01 � � � intr-02 � � � smem
qcom,smem
�CORE_TOP_CSR �� � 0 �
@
@ ipcc
qcom,ipcc ipcc@1103000 qcom,ipcc-protocol � � �MPROC � � y D ! " # : ; - . 9 @ � ipcc@11c1000 qcom,ipcc-protocol � � �COMPUTE_L0 � � N D ! " #
/ 9 - . @ � ipcc@1281000 qcom,ipcc-protocol � � �COMPUTE_L1 � � � D ! " #
/ 9 - . @ � ipcc@1341000 qcom,ipcc-protocol � � �PERIPH � � � (
! " # - @ � ipcc@1401000 qcom,ipcc-protocol � � �FENCE � � � d ! " #
/ 9 � � � � � � � � - . @ � ipcc_legacy@6888004 �� @ � ipcc_legacy_sdc qcom,ipcc-legacy $ � � � 8 9 : ; + � @ timetick timer@68a2000 qcom,timetick �� 4SystemTimer ?$� J T @ � timer@68a3000 qcom,timetick ��0 4WakeUpTimer ?$� J T @ � pinctrl@f100000 $ qcom,kaanapali-pinctrl qcom,pinctrl � � d � k q � � � � > O V B u � � } P �summary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 � �GPIOINTADSP @ � ibi_i3c_qup1_se4_scl � % @ ibi_i3c_qup1_se4_sda � $ @ ibi_i3c_qup1_se7_scl � = @ # ibi_i3c_qup1_se7_sda � < @ " ibi_i3c_qup2_se0_scl � @ ) ibi_i3c_qup2_se0_sda � @ ( ibi_i3c_qup2_se1_scl � @ / ibi_i3c_qup2_se1_sda � @ . ibi_i3c_qup3_se1_scl � @ � ibi_i3c_qup3_se1_sda � @ � ibi_i3c_qup3_se2_scl �
@ � ibi_i3c_qup3_se2_sda � @ � ibi_i3c_qup4_se0_scl � 1 @ Y ibi_i3c_qup4_se0_sda � 0 @ X ibi_i3c_qup4_se1_scl � @ _ ibi_i3c_qup4_se1_sda � @ ^ ibi_i3c_qup4_se2_scl � ! @ e ibi_i3c_qup4_se2_sda � @ d qup1_se0_l0 � P @ qup1_se0_l1 � S @ qup1_se0_l2 � R @ qup1_se0_l3 � Q @ qup1_se1_l0 � J @ qup1_se1_l1 � K @ qup1_se1_l2 � L @ qup1_se1_l3 � M @ qup1_se2_l0 � ( @
qup1_se2_l1 � ) @ qup1_se2_l2 � * @ qup1_se2_l3 � + @
qup1_se2_l4 � � @ � qup1_se2_l5 � � @ � qup1_se2_l6 � � @ � qup1_se3_l0 � , @ qup1_se3_l1 � - @ qup1_se3_l2 � . @ qup1_se3_l3 � / @ qup1_se4_l0 � $ @ qup1_se4_l1 � % @ qup1_se4_l2 � & @ qup1_se4_l3 � ' @ qup1_se5_l0 � 4 @ qup1_se5_l1 � 5 @ qup1_se5_l2 � 6 @ qup1_se5_l3 � 7 @ qup1_se6_l0 � 8 @ qup1_se6_l1 � 9 @ qup1_se6_l2 � : @ qup1_se6_l3 � ; @ qup1_se7_l0 � < @ qup1_se7_l1 � = @ ! qup1_se7_l2 � > @ $ qup1_se7_l3 � ? @ % qup2_se0_l0 � @ & qup2_se0_l1 � @ ' qup2_se0_l2 � @ * qup2_se0_l3 � @ + qup2_se1_l0 � @ , qup2_se1_l1 � @ - qup2_se1_l2 � @ 0 qup2_se1_l3 � @ 1 qup2_se2_l0 � u @ 2 qup2_se2_l1 � v @ 3 qup2_se2_l2 � w @ 4 qup2_se2_l3 � x @ 5 qup2_se3_l0 � z @ 6 qup2_se3_l1 � { @ 7 qup2_se3_l2 � | @ 8 qup2_se3_l3 � } @ 9 qup2_se4_l0 � � @ : qup2_se4_l1 � � @ ; qup2_se4_l2 � � @ < qup2_se4_l3 � � @ = qup3_se0_l0 � @ @ > qup3_se0_l1 � A @ ? qup3_se0_l2 � @ @ @ qup3_se0_l3 � A @ A qup3_se1_l0 � @ B qup3_se1_l1 � @ C qup3_se1_l2 �
@ D qup3_se1_l3 � @ E qup3_se1_l4 �
@ � qup3_se1_l5 � @ � qup3_se1_l6 � @ � qup3_se2_l0 � @ F qup3_se2_l1 �
@ G qup3_se2_l2 � @ H qup3_se2_l3 � @ I qup3_se3_l0 � @ J qup3_se3_l1 � @ K qup3_se3_l2 � @ L qup3_se3_l3 � @ M qup3_se4_l0 � @ N qup3_se4_l1 � @ O qup3_se4_l2 � @ P qup3_se4_l3 � @ Q qup3_se4_l6 � @ � qup3_se5_l0 � @ R qup3_se5_l1 � @ S qup3_se5_l2 � @ T qup3_se5_l3 � @ U qup4_se0_l0 � 0 @ V qup4_se0_l1 � 1 @ W qup4_se0_l2 � 2 @ Z qup4_se0_l3 � 3 @ [ qup4_se1_l0 � @ \ qup4_se1_l1 � @ ] qup4_se1_l2 � @ ` qup4_se1_l3 � @ a qup4_se2_l0 � @ b qup4_se2_l1 � ! @ c qup4_se2_l2 � " @ f qup4_se2_l3 � # @ g qup4_se3_l0 � y @ h qup4_se3_l1 � T @ i qup4_se3_l2 � y @ j qup4_se3_l3 � T @ k qup4_se4_l0 � � @ l qup4_se4_l1 � � @ m qup4_se4_l2 � � @ n qup4_se4_l3 � � @ o top_qup1_se0_i2c_active � �
�
@ top_qup1_se0_i2c_sleep � � � @ top_qup1_se0_spi_active � X X X X @ top_qup1_se0_spi_sleep � � ! � ! � ! � ! @ top_qup1_se0_uart_active � � � � � @ top_qup1_se0_uart_sleep � � � � � @ top_qup1_se1_i2c_active � �
�
@ top_qup1_se1_i2c_sleep � � � @ top_qup1_se1_spi_active � X X X X @ top_qup1_se1_spi_sleep � � ! � ! � ! � ! @ ! top_qup1_se1_uart_active � � � � � @ " top_qup1_se1_uart_sleep � � � � � @ # top_qup1_se2_i2c_active �
�
�
@ $ top_qup1_se2_i2c_sleep �
� � @ % top_qup1_se2_spi_active �
X X X
X @ & top_qup1_se2_spi_sleep �
� ! � ! � !
� ! @ ' top_qup1_se2_uart_active �
� � �
� @ ( top_qup1_se2_uart_sleep �
� � �
� @ ) top_qup1_se3_i2c_active � �
�
@ * top_qup1_se3_i2c_sleep � � � @ + top_qup1_se3_spi_active � X X X X @ , top_qup1_se3_spi_sleep � � ! � ! � ! � ! @ - top_qup1_se3_uart_active � � � � � @ . top_qup1_se3_uart_sleep � � � � � @ / top_qup1_se4_i2c_active � �
�
@ 0 top_qup1_se4_i2c_sleep � � � @ 1 top_qup1_se4_i3c_active � �
�
@ 2 top_qup1_se4_i3c_sleep � � ! � ! @ 3 top_qup1_se4_i3c_ibi_active � �
�
@ 4 top_qup1_se4_i3c_ibi_sleep � � ! � ! @ 5 top_qup1_se4_spi_active � X X X X @ 6 top_qup1_se4_spi_sleep � � ! � ! � ! � ! @ 7 top_qup1_se4_uart_active � � � � � @ 8 top_qup1_se4_uart_sleep � � � � � @ 9 top_qup1_se5_i2c_active � �
�
@ : top_qup1_se5_i2c_sleep � � � @ ; top_qup1_se5_spi_active � X X X X @ < top_qup1_se5_spi_sleep � � ! � ! � ! � ! @ = top_qup1_se5_uart_active � � � � � @ > top_qup1_se5_uart_sleep � � � � � @ ? top_qup1_se6_i2c_active � �
�
@ @ top_qup1_se6_i2c_sleep � � � @ A top_qup1_se6_spi_active � X X X X @ B top_qup1_se6_spi_sleep � � ! � ! � ! � ! @ C top_qup1_se6_uart_active � � � � � @ D top_qup1_se6_uart_sleep � � � � � @ E top_qup1_se7_i2c_active � �
! �
@ F top_qup1_se7_i2c_sleep � � ! � @ G top_qup1_se7_i3c_active � �
! �
@ H top_qup1_se7_i3c_sleep � � ! ! � ! @ I top_qup1_se7_i3c_ibi_active � " �
# �
@ J top_qup1_se7_i3c_ibi_sleep � " � ! # � ! @ K top_qup1_se7_spi_active � X !X $X %X @ L top_qup1_se7_spi_sleep � � ! ! � ! $ � ! % � ! @ M top_qup1_se7_uart_active � � ! � $ � % � @ N top_qup1_se7_uart_sleep � � ! � $ � % � @ O top_qup2_se0_i2c_active � & �
' �
@ P top_qup2_se0_i2c_sleep � & � ' � @ Q top_qup2_se0_i3c_active � & �
' �
@ R top_qup2_se0_i3c_sleep � & � ! ' � ! @ S top_qup2_se0_i3c_ibi_active � ( �
) �
@ T top_qup2_se0_i3c_ibi_sleep � ( � ! ) � ! @ U top_qup2_se0_spi_active � &X 'X *X +X @ V top_qup2_se0_spi_sleep � & � ! ' � ! * � ! + � ! @ W top_qup2_se0_uart_active � & � ' � * � + � @ X top_qup2_se0_uart_sleep � & � ' � * � + � @ Y top_qup2_se1_i2c_active � , �
- �
@ Z top_qup2_se1_i2c_sleep � , � - � @ [ top_qup2_se1_i3c_active � , �
- �
@ \ top_qup2_se1_i3c_sleep � , � ! - � ! @ ] top_qup2_se1_i3c_ibi_active � . �
/ �
@ ^ top_qup2_se1_i3c_ibi_sleep � . � ! / � ! @ _ top_qup2_se1_spi_active � ,X -X 0X 1X @ ` top_qup2_se1_spi_sleep � , � ! - � ! 0 � ! 1 � ! @ a top_qup2_se1_uart_active � , � - � 0 � 1 � @ b top_qup2_se1_uart_sleep � , � - � 0 � 1 � @ c top_qup2_se2_i2c_active � 2 �
3 �
@ d top_qup2_se2_i2c_sleep � 2 � 3 � @ e top_qup2_se2_spi_active � 2X 3X 4X 5X @ f top_qup2_se2_spi_sleep � 2 � ! 3 � ! 4 � ! 5 � ! @ g top_qup2_se2_uart_active � 2 � 3 � 4 � 5 � @ h top_qup2_se2_uart_sleep � 2 � 3 � 4 � 5 � @ i top_qup2_se3_i2c_active � 6 �
7 �
@ j top_qup2_se3_i2c_sleep � 6 � 7 � @ k top_qup2_se3_spi_active � 6X 7X 8X 9X @ l top_qup2_se3_spi_sleep � 6 � ! 7 � ! 8 � ! 9 � ! @ m top_qup2_se3_uart_active � 6 � 7 � 8 � 9 � @ n top_qup2_se3_uart_sleep � 6 � 7 � 8 � 9 � @ o top_qup2_se4_i2c_active � : �
; �
@ p top_qup2_se4_i2c_sleep � : � ; � @ q top_qup2_se4_spi_active � :X ;X <X =X @ r top_qup2_se4_spi_sleep � : � ! ; � ! < � ! = � ! @ s top_qup2_se4_uart_active � : � ; � < � = � @ t top_qup2_se4_uart_sleep � : � ; � < � = � @ u top_qup3_se0_i2c_active � > �
? �
@ v top_qup3_se0_i2c_sleep � > � ? � @ w top_qup3_se0_spi_active � >X ?X @X AX @ x top_qup3_se0_spi_sleep � > � ! ? � ! @ � ! A � ! @ y top_qup3_se0_uart_active � > � ? � @ � A � @ z top_qup3_se0_uart_sleep � > � ? � @ � A � @ { top_qup3_se1_i2c_active � B �
C �
@ | top_qup3_se1_i2c_sleep � B � C � @ } top_qup3_se1_spi_active � BX CX DX EX @ ~ top_qup3_se1_spi_sleep � B � ! C � ! D � ! E � ! @ top_qup3_se1_uart_active � B � C � D � E � @ � top_qup3_se1_uart_sleep � B � C � D � E � @ � top_qup3_se2_i2c_active � F �
G �
@ � top_qup3_se2_i2c_sleep � F � G � @ � top_qup3_se2_spi_active � FX GX HX IX @ � top_qup3_se2_spi_sleep � F � ! G � ! H � ! I � ! @ � top_qup3_se2_uart_active � F � G � H � I � @ � top_qup3_se2_uart_sleep � F � G � H � I � @ � top_qup3_se3_i2c_active � J �
K �
@ � top_qup3_se3_i2c_sleep � J � K � @ � top_qup3_se3_spi_active � JX KX LX MX @ � top_qup3_se3_spi_sleep � J � ! K � ! L � ! M � ! @ � top_qup3_se3_uart_active � J � K � L � M � @ � top_qup3_se3_uart_sleep � J � K � L � M � @ � top_qup3_se4_i2c_active � N �
O �
@ � top_qup3_se4_i2c_sleep � N � O � @ � top_qup3_se4_spi_active � NX OX PX QX @ � top_qup3_se4_spi_sleep � N � ! O � ! P � ! Q � ! @ � top_qup3_se4_uart_active � N � O � P � Q � @ � top_qup3_se4_uart_sleep � N � O � P � Q � @ � top_qup3_se5_i2c_active � R �
S �
@ � top_qup3_se5_i2c_sleep � R � S � @ � top_qup3_se5_spi_active � RX SX TX UX @ � top_qup3_se5_spi_sleep � R � ! S � ! T � ! U � ! @ � top_qup3_se5_uart_active � R � S � T � U � @ � top_qup3_se5_uart_sleep � R � S � T � U � @ � top_qup4_se0_i2c_active � V �
W �
@ � top_qup4_se0_i2c_sleep � V � W � @ � top_qup4_se0_i3c_active � V �
W �
@ � top_qup4_se0_i3c_sleep � V � ! W � ! @ � top_qup4_se0_i3c_ibi_active � X �
Y �
@ � top_qup4_se0_i3c_ibi_sleep � X � ! Y � ! @ � top_qup4_se0_spi_active � VX WX ZX [X @ � top_qup4_se0_spi_sleep � V � ! W � ! Z � ! [ � ! @ � top_qup4_se0_uart_active � V � W � Z � [ � @ � top_qup4_se0_uart_sleep � V � W � Z � [ � @ � top_qup4_se1_i2c_active � \ �
] �
@ � top_qup4_se1_i2c_sleep � \ � ] � @ � top_qup4_se1_i3c_active � \ �
] �
@ � top_qup4_se1_i3c_sleep � \ � ! ] � ! @ � top_qup4_se1_i3c_ibi_active � ^ �
_ �
@ � top_qup4_se1_i3c_ibi_sleep � ^ � ! _ � ! @ � top_qup4_se1_spi_active � \X ]X `X aX @ � top_qup4_se1_spi_sleep � \ � ! ] � ! ` � ! a � ! @ � top_qup4_se1_uart_active � \ � ] � ` � a � @ � top_qup4_se1_uart_sleep � \ � ] � ` � a � @ � top_qup4_se2_i2c_active � b �
c �
@ � top_qup4_se2_i2c_sleep � b � c � @ � top_qup4_se2_i3c_active � b �
c �
@ � top_qup4_se2_i3c_sleep � b � ! c � ! @ � top_qup4_se2_i3c_ibi_active � d �
e �
@ � top_qup4_se2_i3c_ibi_sleep � d � ! e � ! @ � top_qup4_se2_spi_active � bX cX fX gX @ � top_qup4_se2_spi_sleep � b � ! c � ! f � ! g � ! @ � top_qup4_se2_uart_active � b � c � f � g � @ � top_qup4_se2_uart_sleep � b � c � f � g � @ � top_qup4_se3_i2c_active � h �
i �
@ � top_qup4_se3_i2c_sleep � h � i � @ � top_qup4_se3_spi_active � hX iX jX kX @ � top_qup4_se3_spi_sleep � h � ! i � ! j � ! k � ! @ � top_qup4_se3_uart_active � h � i � j � k � @ � top_qup4_se3_uart_sleep � h � i � j � k � @ � top_qup4_se4_i2c_active � l �
m �
@ � top_qup4_se4_i2c_sleep � l � m � @ � top_qup4_se4_spi_active � lX mX nX oX @ � top_qup4_se4_spi_sleep � l � ! m � ! n � ! o � ! @ � top_qup4_se4_uart_active � l � m � n � o � @ � top_qup4_se4_uart_sleep � l � m � n � o � @ � pinctrl@7760000 $ qcom,kaanapali-pinctrl qcom,pinctrl �v d k � � � \ E E E E E E E E E E E E E E E E E E E E E E E @ � slimbus_clk � @ p slimbus_data � @ q slimbus_default_gpio_cfg � p � ! q� ! @ � pinctrl@75C0000 $ qcom,kaanapali-pinctrl qcom,pinctrl �\ d - k q � � � a a Q Q a a a a a a a a a a I E Q Q E E a a Q Q E E E E E E E E E E E E E E Q Q Q Q E E E @ � ssc_gpio_10_clk �
@ � ssc_gpio_11_clk � @ � ssc_gpio_12_clk � @ � ssc_gpio_13_clk �
@ � ssc_gpio_14_clk � @ � ssc_gpio_15_clk � @ � ssc_gpio_18_clk � @ � ssc_gpio_19_clk � @ � ssc_gpio_26_clk � @ � ssc_gpio_27_clk � @ � ssc_gpio_30_clk � @ � ssc_gpio_31_clk � @ � ssc_gpio_32_clk � @ � ssc_gpio_33_clk � ! @ � ssc_gpio_34_clk � " @ � ssc_gpio_35_clk � # @ � ssc_gpio_6_clk � @ � ssc_gpio_7_clk � @ � ssc_qup0_se0_l0 � @ r ssc_qup0_se0_l1 � @ s ssc_qup0_se1_l0 � @ t ssc_qup0_se1_l1 � @ u ssc_qup0_se2_l0 � @ v ssc_qup0_se2_l1 � @ w ssc_qup0_se2_l2 � @ x ssc_qup0_se2_l3 � @ y ssc_qup0_se2_l4 � @ � ssc_qup0_se2_l5 � @ � ssc_qup0_se3_l0 � @ z ssc_qup0_se3_l1 � @ { ssc_qup0_se4_l0 �
@ | ssc_qup0_se4_l1 � @ } ssc_qup0_se4_l2 � @ ~ ssc_qup0_se4_l3 �
@ ssc_qup0_se4_l4 � @ � ssc_qup0_se4_l5 � @ � ssc_qup0_se5_l0 � @ � ssc_qup0_se5_l1 � @ � ssc_qup0_se5_l2 � @ � ssc_qup0_se5_l3 � @ � ssc_qup0_se6_l0 � @ � ssc_qup0_se6_l1 � @ � ssc_qup0_se6_l2 � @ � ssc_qup0_se6_l3 � @ � ssc_qup0_se7_l0 � @ � ssc_qup0_se7_l1 � @ � ssc_qup0_se7_l2 � @ � ssc_qup0_se7_l3 � @ � ssc_qup1_se0_l0 � @ � ssc_qup1_se0_l1 � @ � ssc_qup1_se1_l0 � @ � ssc_qup1_se1_l1 � @ � ssc_qup1_se2_l0 � @ � ssc_qup1_se2_l1 � @ � ssc_qup1_se2_l2 � @ � ssc_qup1_se2_l3 � @ � ssc_qup1_se3_l0 � @ � ssc_qup1_se3_l1 � @ � ssc_qup1_se4_l0 � @ � ssc_qup1_se4_l1 � @ � ssc_qup1_se5_l0 � @ � ssc_qup1_se5_l1 � ! @ � ssc_qup1_se5_l2 � " @ � ssc_qup1_se5_l3 � # @ � ssc_qup1_se6_l0 � $ @ � ssc_qup1_se6_l1 � % @ � ssc_qup1_se6_l2 � $ @ � ssc_qup1_se6_l3 � % @ � qup_ssc0_se0_i2c_active � r �
s �
@ � qup_ssc0_se0_i2c_sleep � r � s � @ � qup_ssc0_se0_i3c_active � r �
s �
@ � qup_ssc0_se0_i3c_sleep � r � ! s � ! @ � qup_ssc0_se0_i3c_ibi_active � r �
s �
@ � qup_ssc0_se0_i3c_ibi_sleep � r � ! s � ! @ � qup_ssc0_se1_i2c_active � t �
u �
@ � qup_ssc0_se1_i2c_sleep � t � u � @ � qup_ssc0_se1_i3c_active � t �
u �
@ � qup_ssc0_se1_i3c_sleep � t � ! u � ! @ � qup_ssc0_se1_i3c_ibi_active � t �
u �
@ � qup_ssc0_se1_i3c_ibi_sleep � t � ! u � ! @ � qup_ssc0_se2_i2c_active � v �
w �
@ � qup_ssc0_se2_i2c_sleep � v � w � @ � qup_ssc0_se2_i3c_active � v �
w �
@ � qup_ssc0_se2_i3c_sleep � v � ! w � ! @ � qup_ssc0_se2_i3c_ibi_active � v �
w �
@ � qup_ssc0_se2_i3c_ibi_sleep � v � ! w � ! @ � qup_ssc0_se2_spi_active � vX wX xX yX @ � qup_ssc0_se2_spi_sleep � v � ! w � ! x � ! y � ! @ � qup_ssc0_se2_spi_3w_sleep � w � ! x � ! y � ! @ � qup_ssc0_se2_spi_3w_active � wX xX yX
@ � qup_ssc0_se3_i2c_active � z �
{ �
@ � qup_ssc0_se3_i2c_sleep � z � { � @ � qup_ssc0_se3_i3c_active � z �
{ �
@ � qup_ssc0_se3_i3c_sleep � z � ! { � ! @ � qup_ssc0_se3_i3c_ibi_active � z �
{ �
@ � qup_ssc0_se3_i3c_ibi_sleep � z � ! { � ! @ � qup_ssc0_se4_i2c_active � | �
} �
@ � qup_ssc0_se4_i2c_sleep � | � } � @ � qup_ssc0_se4_spi_active � |X }X ~X X @ � qup_ssc0_se4_spi_sleep � | � ! } � ! ~ � ! � ! @ � qup_ssc0_se4_spi_3w_active � }X ~X X
@ � qup_ssc0_se4_spi_3w_sleep � } � ! ~ � ! � ! @ � qup_ssc0_se5_i2c_active � � �
� �
@ � qup_ssc0_se5_i2c_sleep � � � � � @ � qup_ssc0_se5_spi_active � �X �X �X �X @ � qup_ssc0_se5_spi_sleep � � � ! � � ! � � ! � � ! @ � qup_ssc0_se5_spi_3w_active � �X �X �X
@ � qup_ssc0_se5_spi_3w_sleep � � � ! � � ! � � ! @ � qup_ssc0_se5_uart_active � � � � � � � � � @ � qup_ssc0_se5_uart_sleep � � � � � � � � � @ � qup_ssc0_se6_i2c_active � � �
� �
@ � qup_ssc0_se6_i2c_sleep � � � � � @ � qup_ssc0_se6_i3c_active � � �
� �
@ � qup_ssc0_se6_i3c_sleep � � � ! � � ! @ � qup_ssc0_se6_i3c_ibi_active � � �
� �
@ � qup_ssc0_se6_i3c_ibi_sleep � � � ! � � ! @ � qup_ssc0_se6_uart_active � � � � � � � � � @ � qup_ssc0_se6_uart_sleep � � � � � � � � � @ � qup_ssc0_se7_i2c_active � � �
� �
@ � qup_ssc0_se7_i2c_sleep � � � � � @ � qup_ssc0_se7_uart_active � � � � � � � � � @ � qup_ssc0_se7_uart_sleep � � � � � � � � � @ � qup_ssc1_se0_i2c_active � � �
� �
@ � qup_ssc1_se0_i2c_sleep � � � � � @ � qup_ssc1_se0_i3c_active � � �
� �
@ � qup_ssc1_se0_i3c_sleep � � � ! � � ! @ � qup_ssc1_se0_i3c_ibi_active � � �
� �
@ � qup_ssc1_se0_i3c_ibi_sleep � � � ! � � ! @ � qup_ssc1_se1_i2c_active � � �
� �
@ � qup_ssc1_se1_i2c_sleep � � � � � @ � qup_ssc1_se1_i3c_active � � �
� �
@ � qup_ssc1_se1_i3c_sleep � � � ! � � ! @ � qup_ssc1_se1_i3c_ibi_active � � �
� �
@ � qup_ssc1_se1_i3c_ibi_sleep � � � ! � � ! @ � qup_ssc1_se2_i2c_active � � �
� �
@ � qup_ssc1_se2_i2c_sleep � � � � � @ � qup_ssc1_se2_i3c_active � � �
� �
@ � qup_ssc1_se2_i3c_sleep � � � ! � � ! @ � qup_ssc1_se2_i3c_ibi_active � � �
� �
@ � qup_ssc1_se2_i3c_ibi_sleep � � � ! � � ! @ � qup_ssc1_se2_spi_active � �X �X �X �X @ � qup_ssc1_se2_spi_sleep � � � ! � � ! � � ! � � ! @ � qup_ssc1_se2_spi_3w_active � �X �X �X
@ � qup_ssc1_se2_spi_3w_sleep � � � ! � � ! � � ! @ qup_ssc1_se3_i2c_active � � �
� �
@ qup_ssc1_se3_i2c_sleep � � � � � @ qup_ssc1_se3_i3c_active � � �
� �
@ qup_ssc1_se3_i3c_sleep � � � ! � � ! @ qup_ssc1_se3_i3c_ibi_active � � �
� �
@ qup_ssc1_se3_i3c_ibi_sleep � � � ! � � ! @ qup_ssc1_se4_i2c_active � � �
� �
@ qup_ssc1_se4_i2c_sleep � � � � � @ qup_ssc1_se5_i2c_active � � �
� �
@ qup_ssc1_se5_i2c_sleep � � � � � @
qup_ssc1_se5_spi_active � �X �X �X �X @ qup_ssc1_se5_spi_sleep � � � ! � � ! � � ! � � ! @ qup_ssc1_se5_spi_3w_active � �X �X �X
@
qup_ssc1_se5_spi_3w_sleep � � � ! � � ! � � ! @ qup_ssc1_se6_i2c_active � � �
� �
@ qup_ssc1_se6_i2c_sleep � � � � � @ qup_ssc1_se6_i3c_active � � �
� �
@ qup_ssc1_se6_i3c_sleep � � � ! � � ! @ qup_ssc1_se6_i3c_ibi_active � � �
� �
@ qup_ssc1_se6_i3c_ibi_sleep � � � ! � � ! @ qup_ssc1_se6_uart_active � � � � � � � � � @ qup_ssc1_se6_uart_sleep � � � � � � � � � @ vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx ! 9 � Q jmx.lvl } � � @ � vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc ! 9 � Q jmxc.lvl } � � @ � vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx ! 9 � Q jcx.lvl } � � @ � vdd_lpi_mx qcom,rpmh-arc-regulator /vcs/vdd_lpi_mx /vcs/vdd_ssc_mx ! 9 � Q jlmx.lvl } � �?�� @ � vdd_lpi_cx qcom,rpmh-arc-regulator ! /vcs/vdd_lpi_cx /vcs/vdd_ssc_int ! 9 � Q jlcx.lvl } � �?�� @ � clock-controller@100000 % qcom,gcc-kaanapali qcom,cc-kaanapali � � 0 @ P ` p � � � � � � � / B / B � �GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_GPLL10_CM_PLL_TAYCAN_COMMON GCC_GPLL11_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ11_200_CL36L12_LE GCC_RPU_XPU4 � @ clock-controller@1f40000 . qcom,lpass_aon_cc-kaanapali qcom,cc-kaanapali P �� � � � �� � �` �p � &� < �TCSR_TCSR_REGS LPASS_QDSP6SS_QDSP6SS_PUB LPASS_QDSP6SS_QDSP6SS_QDSP6SSV81_CORE_CC_SWI LPASS_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON LPASS_QDSP6SS_QDSP6SSV81_CORE_CC_REG LPASS_AON_CC_PLL_CM_PLL_TAYCAN_COMMON LPASS_AON_CC_AHB2PHY_SWMAN LPASS_AON_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_CC_LPASS_AON_CC_REG LPASS_LPI_TCM_REG � @ � clock-controller@7700000 1 qcom,lpass_aon_mx_cc-kaanapali qcom,cc-kaanapali �p p` pp p� � � �LPASS_AON_MX_CC_RO_PLL_CM_PLL_PONGO_COMMON LPASS_AON_MX_CC_AHB2PHY_SWMAN LPASS_AON_MX_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_MX_CC_LPASS_AON_MX_CC_REG � @ � clock-controller@6bc0000 0 qcom,lpass_audio_cc-kaanapali qcom,cc-kaanapali 0 �� � � �` �p �� � �LPASS_AUDIO_CC_PLL_CM_PLL_ZONDA_COMMON LPASS_AUDIO_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_AUDIO_CC_LCC_PLL_CM_PLL_JBIST4_COMMON LPASS_AUDIO_CC_AHB2PHY_SWMAN LPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AUDIO_CC_LPASS_AUDIO_CC_REG � @ � clock-controller@7b00000 / qcom,lpass_core_cc-kaanapali qcom,cc-kaanapali 0 �� �` �p �� � 0 � � �LPASS_LPASS_CORE_CC_DIG_PLL_LPASS_CORE_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_LPASS_CORE_CC_REG LPASS_HW_AF_CORE LPASS_CORE_GDSC � @ � clock-controller@6e40000 0 qcom,lpass_lpmla_cc-kaanapali qcom,cc-kaanapali �� �` �p � @ � �LPASS_LPMLA_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPMLA_CC_AHB2PHY_SWMAN LPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPMLA_CC_LPASS_LPMLA_CC_REG � @ � clock-controller@7880000 % qcom,scc-kaanapali qcom,cc-kaanapali �� �SSC_SCC_SCC_SCC_REG � @ � cesta@7213000 - qcom,lpass_cesta-kaanapali qcom,cc-kaanapali ( �!0 !4 !8 !X !^ @ �LPASS_CRMB LPASS_CRMB_PT LPASS_CRMC LPASS_CRMV LPASS_CRM_COMMON @ cxstmtrace@16000000 qcom,stmtrace � � � lpistmtrace@7100000 qcom,stmtrace � � � @ cxstmcfg@10002000 qcom,stmcfg � � � � lpistmcfg@11343000 qcom,stmcfg �40 � � � cxetb@11305000 qcom,tmc �0P lpietb@11345000 qcom,tmc �4P tpdm@11350000
qcom,tpdm �5 �tpdm_24 � � � tpdm@11351000
qcom,tpdm �5 �tpdm_31 � � � tpdm@11346000
qcom,tpdm �4` �tpdm_129 � � � tpdm@11334000
qcom,tpdm �3@ �tpdm_90 � � � qdss " 0 /� � � L� � L � !^!^ 8� H � S c � tpath_lpass_lpi_dl_tpda � � � � @ � tpath_lpass_lpi_audio_hm_dl_tpda � � � � @ � tpath_lpi_stm � � � � @ � tpath_lpi_etm � � � � @ � tpath_sdc_etm � � � @ � tpath_stm � � � @ � tpath_sdc_itm � � � @ � tpath_lpass_lpi_noc � � � @ � tpath_lpi_aon_noc � � � @ � tpath_aoc � � � @ � tpath_enpu0_noc � � � � @ � tpath_enpu1_noc � � � � @ � cti@11354000 qcom,cti " �lpass_lpi_cti_3_cti_3_qc_cti_core �5@ cti@1134b000 qcom,cti & �lpass_lpi_qdsp6_qdsp6ss_qdsp6ss_cscti �4� cti@11342000 qcom,cti $ �lpass_lpi_cti_sdc_2_cti_sdc_2_cscti �4 cti@11335000 qcom,cti " �ddrss_lpi_cti_cti_qc_cti_extended �3P cti@11341000 qcom,cti " �lpass_lpi_cti_1_cti_1_qc_cti_core �4 qdss_lpi_csr@6ee0000 qcom,qdss_lpi_csr �� funnel@10041000
qcom,tfunnel � @ � funnel@11353000
qcom,tfunnel �50 @ � funnel@11304000
qcom,tfunnel �0@ @ � funnel@11344000
qcom,tfunnel �4@ @ � tnoc@11331000
qcom,tnoc � � �3 � * � � # �port_ddrss_lpi_ddrss_lpi_trace_noc @ � port_lpi_stm qcom,gts � � � port_lpi_etm qcom,gts � � � port_sdc_etm qcom,gts � � � port_stm qcom,gts � � � port_sdc_itm qcom,gts � � � port_lpass_lpi_noc qcom,gts � � � port_lpi_aon_noc qcom,gts � � � port_aoc qcom,gts �
� � port_enpu0_noc qcom,gts � � � port_enpu1_noc qcom,gts � � � tpda@11352000
qcom,tpda �5
�lpass-lpi � � � � @ � tpda@11347000
qcom,tpda �4p �lpass-audio � 8 � � � @ � subsys_instance qcom,subsys_instance � systemcache@31800000 qcom,systemcache 0 �1� 1� 2� 2� 4� 4� S �llcc0_base llcc1_base llcc2_base llcc3_base llcc_bcast_or_base llcc_bcast_and_base � @ � � @ � llc-island qcom,llc-island islands �� island@c,ff800000 � �� | kam-llc-island qcom,llc-island islands �� island@c,ff800000 � �� \ ssc_qup_fw_cfg qcom,qupfw-controller ssc_qup_0 se0_cfg $ P & / @ N [ c k se1_cfg $ @ Q & / @ N [ c k se2_cfg $ � R & / @ N [ c k se3_cfg $ � S & / @ N [ c k se4_cfg $ & / @ N� [ c k se5_cfg $ @ & / @ N� [ c k se6_cfg $ � T & / @ N [ c k se7_cfg $ � & / @ N� [ c k ssc_qup_1 se0_cfg $ U & / @ N [ c k se1_cfg $ @ V & / @ N [ c k se2_cfg $ � W & / @ N [ c k se3_cfg $ � X & / @ N [ c k se4_cfg $ & / @ N� [ c k se5_cfg $ @ & / @ N� [ c k se6_cfg $ � Y & / @ N [ c k ssc_ibi_cd_domains qcom,ssc-pwr-domain-controller tibi_cd0 ibi_cd1 ibi_cd2 � �Q� � ��f�� ��-�� @ ibi_ssc_0_cfg@7500000 qcom,ibi-controller �P � n � � G � ! �ok @ ibi_ssc_1_cfg@7510000 qcom,ibi-controller �Q � n � � f � �ok @ ibi_ssc_2_cfg@7520000 qcom,ibi-controller �R � n � � � � �ok @ ibi_ssc_3_cfg@7530000 qcom,ibi-controller �S � n � � � � � �ok @ ibi_ssc_4_cfg@7540000 qcom,ibi-controller �T � n � � � � � �ok @ ibi_ssc_5_cfg@7550000 qcom,ibi-controller �U � n � � � � � �ok @ ibi_ssc_6_cfg@7560000 qcom,ibi-controller �V � n � � � � � �ok @ ibi_ssc_7_cfg@7570000 qcom,ibi-controller �W � n � � � � � �ok @ ibi_ssc_8_cfg@7580000 qcom,ibi-controller �X � n � � � � � �ok @
ibi_ssc_9_cfg@7590000 qcom,ibi-controller �Y � n � � � � � �ok @ ibi_top_0_cfg@EC90000 qcom,ibi-controller �� � n � � 9 � ; �ok @ ibi_top_1_cfg@ECA0000 qcom,ibi-controller �� � n � � � �ok @
ibi_top_2_cfg@ECB0000 qcom,ibi-controller �� � n � � < � C �ok @ ibi_top_3_cfg@ECC0000 qcom,ibi-controller �� � n � � # � ' �ok @ ibi_top_4_cfg@ECD0000 qcom,ibi-controller �� � n � � Q � R �ok @ ibi_top_5_cfg@ECE0000 qcom,ibi-controller �� � n � � * � 3 �ok @ ibi_top_6_cfg@ECF0000 qcom,ibi-controller �� � n � � S � U �ok @ ibi_top_7_cfg@ED00000 qcom,ibi-controller �� � n � � W � _ �ok @ ibi_top_8_cfg@ED10000 qcom,ibi-controller �� � n � � g � h �ok @ ssc_pwr_domains qcom,ssc-pwr-domain-controller tssc_gdsc � �@��H SSC_QUP_0@7900000 qcom,sscqup-controller �� tcore2x core s-ahb m-ahb � �Sd� �d�4 ���v ��^�, � � � ��р � � � �ok SSC_QUP_0_SE_0 qcom,se-controller " R + 5� H ��� \ f {+ � � � � � � � � � � � tse-clk � �H� J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � ' � �ok SSC_QUP_0_SE_1 qcom,se-controller @ " R + 5� H � �� \ f {, � p � � � � � � � � � tse-clk � � �Ǟ J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � ' � �ok SSC_QUP_0_SE_2 qcom,se-controller � " R + 5� H �
�� \ f {- � � � � � � � � � tse-clk � �~E: | �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep spi-3w-default spi-3w-sleep � � � � � � � ' � 1 � ; � E � O � �ok SSC_QUP_0_SE_3 qcom,se-controller � " R + 5� H � �� \ f {. � � � � � � � � � tse-clk � �� �w J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � ' � �ok SSC_QUP_0_SE_4 qcom,se-controller � " R + 5
H � �� \ f {/ � � � � � � � � � tse-clk � �*̉ H �i2c-default i2c-sleep spi-default spi-sleep spi-3w-default spi-3w-sleep � � � � � � � ' � �ok SSC_QUP_0_SE_5 qcom,se-controller @ � " R + 5 H �
�� \ f {0 � w � � � � � � � � � tse-clk � ���� ` �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep � � � � � � � ' � 1 � ; � �ok SSC_QUP_0_SE_6 qcom,se-controller � " R + 5� H ��� \ f {1 � � � � � � � � � � � tse-clk � ��� b �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep uart-default uart-sleep � � � � � � � ' � 1 � ; � �ok SSC_QUP_0_SE_7 qcom,se-controller � � " R + 5 H ��� \ f {* � � � � � � � � � � � tse-clk � ��O�� . �i2c-default i2c-sleep uart-default uart-sleep � � � � � � �ok SSC_QUP_1@7A00000 qcom,sscqup-controller �� tcore2x core s-ahb m-ahb � ���� �Tk�� ��tp � M � � � � ��р � � � �ok SSC_QUP_1_SE_0 qcom,se-controller " R + 5� H ��� \ f {) � � � � � � � � � tse-clk � ���) J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � ' � �ok SSC_QUP_1_SE_1 qcom,se-controller @ " R + 5� H � �� \ f {� � � � � � � � � � tse-clk � ��� J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � ' � �ok SSC_QUP_1_SE_2 qcom,se-controller � " R + 5� H �
�� \ f {� � � � � � � � � � tse-clk � �� �d | �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep spi-3w-default spi-3w-sleep � � � � � � � ' � 1 � ; � E � O �ok SSC_QUP_1_SE_3 qcom,se-controller � " R + 5� H � �� \ f {� � � � � � � � � � tse-clk � �]F�� J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � ' �ok SSC_QUP_1_SE_4 qcom,se-controller � " R + 5 H � �� \ f {� � � � � � � � � � tse-clk � �,�r� �i2c-default i2c-sleep � � �ok SSC_QUP_1_SE_5 qcom,se-controller @ � " R + 5
H �
�� \ f {� � � � � � � � � � tse-clk � ���R* H �i2c-default i2c-sleep spi-default spi-sleep spi-3w-default spi-3w-sleep � �
' �ok SSC_QUP_1_SE_6 qcom,se-controller � " R + 5� H ��� \ f {� � � � � � � � � � tse-clk � �3,�� b �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep uart-default uart-sleep � � ' 1 ; �ok TOP_QUP_1@a00000 qcom,qup-controller � � tcore2x core s-ahb m-ahb � �ۂ� @��� 4(�~ Q�'b � � � ��� � � �ok TOP_QUP_1_SE_0 qcom,se-controller � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � � > D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � ' �ok TOP_QUP_1_SE_1 qcom,se-controller @ � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � ދڬ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � ! " ' # �ok TOP_QUP_1_SE_2 qcom,se-controller � � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � E�4� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � $ � % & ' ( ' ) �ok TOP_QUP_1_SE_3 qcom,se-controller � � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � l� � D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � * � + , - . ' / �ok TOP_QUP_1_SE_4 qcom,se-controller " 0 R + 5� H �
\ f { � � Y � � � � �� � � tse-clk � *�KF x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � 0 � 1 2 3 4 ' 5 1 6 ; 7 E 8 O 9 �ok TOP_QUP_1_SE_5 qcom,se-controller @ � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � �y� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � : � ; < = > ' ? �ok TOP_QUP_1_SE_6 qcom,se-controller � � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � o�&j D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � @ � A B C D ' E �ok TOP_QUP_1_SE_7 qcom,se-controller � " 0 R + 5� H � \ f { � � Y � � � � �� � � tse-clk � �G5� x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � F � G H I J ' K 1 L ; M E N O O �ok TOP_QUP_2@800000 qcom,qup-controller � � tcore2x core s-ahb m-ahb � p�i �_h� 0n�U ��~t � � � ��� � � �ok TOP_QUP_2_SE_0 qcom,se-controller " 0 R + 5� H �
\ f { � � Y � � � � �� � � tse-clk � b8� x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � P � Q R S T ' U 1 V ; W E X O Y �ok TOP_QUP_2_SE_1 qcom,se-controller @ " 0 R + 5� H � \ f { � � Y � � � � �� � � tse-clk � �'�� x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � Z � [ \ ] ^ ' _ 1 ` ; a E b O c �ok TOP_QUP_2_SE_2 qcom,se-controller � � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � ��+ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � d � e f g h ' i �ok TOP_QUP_2_SE_3 qcom,se-controller � � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � �,y D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � j � k l m n ' o �ok TOP_QUP_2_SE_4 qcom,se-controller � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � y��~ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � p � q r s t ' u �ok TOP_QUP_3@1900000 qcom,qup-controller �� tcore2x core s-ahb m-ahb � ���e �J �7�i 6�<� � � � ��� � � �ok TOP_QUP_3_SE_0 qcom,se-controller � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � ���= D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � v � w x y z ' { �ok TOP_QUP_3_SE_1 qcom,se-controller @ � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � B� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � | � } ~ � ' � �ok TOP_QUP_3_SE_2 qcom,se-controller � � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � �+ o D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok TOP_QUP_3_SE_3 qcom,se-controller � � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � oP�� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok TOP_QUP_3_SE_4 qcom,se-controller " 0 � R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � d� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok TOP_QUP_3_SE_5 qcom,se-controller @ " 0 � R + 5 H � \ f { � � Y � � � � �� � � tse-clk � ��� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok TOP_QUP_4@1a00000 qcom,qup-controller �� tcore2x core s-ahb m-ahb � -�� z��� �� y P풧 � � � ��� � � �ok TOP_QUP_4_SE_0 qcom,se-controller " 0 R + 5� H �
\ f { � � Y � � � � �� � � tse-clk � n� x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � 1 � ; � E � O � �ok TOP_QUP_4_SE_1 qcom,se-controller @ " 0 R + 5� H � \ f { � � Y � � � � �� � � tse-clk � 6�VF x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � 1 � ; � E � O � �ok TOP_QUP_4_SE_2 qcom,se-controller � " 0 R + 5� H �
\ f { � � Y � � � � �� � � tse-clk � ���; x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � 1 � ; � E � O � �ok TOP_QUP_4_SE_3 qcom,se-controller � � " 0 R + 5 H � \ f { � � Y � � � � �� � � tse-clk � ��k� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok TOP_QUP_4_SE_4 qcom,se-controller � " 0 R + 5 H �
\ f { � � Y � � � � �� � � tse-clk � �x{; D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � ' � �ok qup_tcsr_info qcom,quptcsr-controller a tcsr_cfg0 n k v ��@ ���D ���@ ���H tcsr_cfg1 n � v ��L ���P ���L ���T SlimbusBSP qcom,smbus-controller � �SLIMBUS � @ �LPASS � � �� ��@ � �
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BUSES_DEBUG n CAMERA_OIS
CAMERA_OIS n SENSORS_OIS
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qcom,err_qdi �P 4
pd_mon audio_process qcom,pd_mon_user_process_config A/ramfs/audio_lpai.mbn 3 V/rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn laudio_process t � � �audio_pd qsh_process qcom,pd_mon_user_process_config A/ramfs/qsh.mbn , V/rfs/root/vendor/firmware_mnt/image/qsh.mbn lqsh_process t � �
�sensor_pd ois_process qcom,pd_mon_user_process_config A/ramfs/ois_lpai.mbn , V/rfs/root/vendor/firmware_mnt/image/ois.mbn lois_process t � � �ois_pd pd_mon_restart qcom,pd_mon_restart � � rcinit qcom,rcinit_cfg rcinit_config_spinor � � �d u0 ! � = � Y � u � � � � � � � � rcinit_config � � !4 � ! � = � Y � u � � � � � � � � servreg
qcom,servreg msm/adsp/root_pd msm &adsp :root_pd Q J sys_m qcom,sys_m i s � tms_dog
qcom,tms_dog ��@ ��@ ��@ ��@ ��@ ��@ ��@ � �� � �� �� * G d y � tms_diag qcom,tms_diag � 0 services tuna dynamic_heap qcom,dynamic_heap client_id_config client_id_00 �DYNAMIC_MEM_CLIENT_ID_SENSOR � client_id_01 �DYNAMIC_MEM_CLIENT_ID_TEST � systemcache qcom,systemcache-sw � � � @ � # - . kam-systemcache qcom,systemcache-sw � � � @ � # - . llc-lpi-dump qcom,llc-lpi-dump 4 �QSH_ISLAND_POOL SSC_ISLAND_POOL QSHTECH_ISLAND_POOL diag qcom,adsp_core_diagcfg diagcfg_cmd � * 8 = V U o Z � � � � � � $ D ] q
� � � �" � � , E Y s �! diagcfg_param � @ � � � �
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� � � � � � 2 - B Z r @ � � � � � � � � � < : Z u � � � � � �K � � ' � G a �d � � � � � . H h � � � � � � @ < = YZ u �QURTOS_ISLAND_POOL �QURTOS_ISLAND_POOL diagcfg_early_log � � _ � � � � � � diagcfg_f3_trace ) � C qdsp_pm config qcom,config_data Y g � lpassRegRange �� � n l2ConfigRegRange � � n cores-array core0 � e � � � � ? � core1 � f � � � � � core2 � g � � � � " � core3 � h � � � � � core4 � i � � � � � core5 � j � � Z � � � core6 � l � � � � ! � core7 � m � � U � � � core8 � o � � � � . � core9 � { � � � � 2 � core10 � r � � � � + � core11 � v � � �
� / � core12 � w � � _ � � � core13 � y � � � � 1 � core14 � z � � � � 0 � core15 � | � � p q � � 6 7 � core16 � � � � l � � � core17 � � � � o � � � core18 � � � � m � � � core19 � � � � n � � 5 � memories-array memory0 � � memory1 � � clocks-array clock0 /clk/cpu $ - � clock1 lpass_core_cc_core_clk $ - � clock2 lpass_audio_cc_bus_clk $ - � clock3 lpass_aon_cc_aon_h_clk $ - � clock4 6 lpass_aon_cc_lpi_noc_ls_clk $ - � clock5 7 lpass_aon_cc_lpi_noc_hs_clk $ - � clock6 lpass_audio_cc_slimbus_core_clk $ - � clock7 lpass_core_cc_lpm_core_clk $ - � clock8 lpass_core_cc_lpm_mem0_core_clk $ - � clock9 lpass_audio_cc_codec_mem_clk $ - � clock10 lpass_audio_cc_codec_mem0_clk $ - � clock11 lpass_audio_cc_codec_mem1_clk $ - � clock12 lpass_audio_cc_codec_mem2_clk $ - � clock13 lpass_audio_cc_codec_mem3_clk $ - � clock14 lpass_aon_mx_cc_va_mem0_clk $ - � clock15 lpass_aon_mx_cc_va_mem1_clk $ - � clock16 $ lpass_core_cc_sysnoc_mport_core_clk $ - � clock17 lpass_audio_cc_bus_timeout_clk $ - � clock18 C ( lpass_aon_cc_lpass_0_lpmla_ahb_odsc_clk $ - � clock19 D ( lpass_aon_cc_lpass_1_lpmla_ahb_odsc_clk $ - � clock20 # lpass_core_cc_sysnoc_sway_core_clk $ - � clock21 ? scc_ccd_ahb2ahb_m_clk $ - � clock22 @ scc_ccd_ahb2ahb_s_clk $ - � clock23 A scc_ahb2ahb_s_clk $ - � clock24 B lpass_aon_mx_cc_ibi_clk $ - � clock25 U lpass_core_cc_resampler_clk $ - � clock26 Z lpass_audio_cc_slimbus_clk $ - � clock27 \ lpass_core_cc_avsync_stc_clk $ - � clock28 ] lpass_core_cc_avsync_atime_clk $ - � clock29 _ lpass_core_cc_hw_af_clk $ - � clock30 ` lpass_core_cc_hw_af_noc_clk $ - � clock31 p ! lpass_lpmla_cc_lpass_0_lpmla_clk $ - � clock32 q ! lpass_lpmla_cc_lpass_1_lpmla_clk $ - � clock33 v lpass_aon_cc_enpu_scheduler_clk $ - � clock34 l lpass_aon_cc_sdc_proc_fclk_clk $ - � clock35 o scc_ccd_clk $ - � clock36 n
scc_smem_clk $ - � busport-array busPort0 6 E L Z g busPort1 6 @ E L Z g busPort2 A 6 @ E L Z � g busPort3 B 6 @ E L Z � g busPort4 C 6 @ E L Z � g busPort5 D 6 @ E L Z � g busPort6 E 6 @ E L Z � g busPort7 6 E L Z � g busPort8 6 E L Z � g busPort9 6 E L Z � g busPort10 6 E L Z � g busPort11 6 @ E L Z � g busPort12 6 E L Z � g busPort13
6 E L Z � g busPort14 6 @ E ` L Z � g busPort15 6 E L Z � g busPort16 6 @ E L Z 1 g busPort17 6 @ E L Z 1 g busPort18 6 E L Z � g busPort19 6 E L Z � g busPort20 6 E L r g $ busPort21 6 E L r g $ busPort22 6 E L r g $ busPort23 6 E L r g $ busPort24 ! 6 E L r g $ busPort25 " 6 E L r g $ busPort26 $ 6 � E L r g $ busPort27 % 6 � E L r � g $ busPort28 ' 6 � E L r ' g $ busPort29 ( 6 � E L r g $ busPort30 + 6 E L r g $ busPort31 1 6 E L r g $ busPort32 0 6 E L r g $ busPort33 . 6 E L r g $ busPort34 2 6 E L r g $ busPort35 / 6 E L r g $ busPort36 6 6 E L C r g $ busPort37 7 6 E L D r g $ busPort38 5 6 E n L r � g 5 busPort39 ? 6 E L r g ? extroute-array extBusRoute0 ~ � % extBusRoute1 ~ A � ( extBusRoute2 ~ � % extBusRoute3 ~ B � ( extBusRoute4 ~ � % extBusRoute5 ~ C � ( extBusRoute6 ~ � % extBusRoute7 ~ D � ( extBusRoute8 ~ � % extBusRoute9 ~ E � ( mipsroute-array mipsBwRoute0 ~ � % mipsBwRoute1 ~ A � ( pwrDomain-array pwrDomain0 � �/core/cpu/latency � � � � pwrDomain1 � ! �lpass_core_cc_lpass_core_hm_gdsc � � � � pwrDomain2 � ! �lpass_aon_cc_lpass_audio_hm_gdsc � � � � pwrDomain3 � � � � � � pwrDomain4 � �lpass_aon_cc_lpass_ssc_gdsc � � � � cestaBw-array client0 � � �lpass path0 �
5 cestaClk-array clk0 l lpass_aon_cc_sdc_proc_fclk_clk cestaPwrDomain-array pwrDomain0 � �lpass_aon_cc_lpass_ssc_gdsc features-array feature0 z � ) � feature1 z ) feature2 z ) feature3 z �� ) ��� feature4 z ) feature5 z ) feature6 z ) feature7 z ) feature8 z � ) ��� feature9 z ) ��� feature10 z 5�� ) ��� feature11 z /�� ) ��� feature12 z ) feature13 z � ) � feature14 z $=X ) ��� feature15 z �� ) '� feature16 z ) feature17 z ) feature18 z ) feature19 z ) feature20 z ) feature21 z ) feature22 z ) feature23 z ) feature24 z ) feature25 z ) feature26 z ) feature27 z ) feature28 z ) feature29 z ) ��� feature30 z ) feature31 z ) feature32 z ) feature33 z ) feature34 z ) feature35 z ) feature36 z ) feature37 z ) config_arch qcom,config_arch compensatedDdrBwTable 0 �� rp� � 0 " �� ��� � 0 ) ܓ� ��� X 0 0 �t� �2� � 0 7 �U� �2� � 0 > &�6� �� � 0 E ,�� s�� � 0 L 2��� �� � 0 S 8�ـ �� � 0 Z >��� �� � 0 a������� �� � adspsnocVoteTable 8 �� ��� � � ' 8 " �� ��� � � ' 8 ) ܓ� ��� X X ' 8 0 �t� �2� � � ' 8 7 �U� e�� � � ' 8 > &�6� �O� � � ' 8 E ,�� �� � � ' 8 L 2��� �� � � ' 8 S 8�ـ �U� � � ' 8 Z >��� *�� � � ' 8 a������� ��� � � ' compensatedLecDdrBwTable 0 �� ��� X 0 " �� �2� � 0 ) � �� � 0 0 ׄ s�� � 0 7 �e �� � 0 >������� �� � adspLecsnocVoteTable 8 �� ��� X 8 " �� �2� � 8 ) � �O� � 8 0 ׄ �� � 8 7 �e �U� � 8 >������� ��� � compensatedMlDdrBwTable 0 �� rp� X 0 " kI� ��� � 0 ) Н� �2� � 0 0 8� �� � 0 7 G�W s�� � 0 > �n! �� � 0 E������� �� � adspMlsnocVoteTable 8 �� ��� X 8 " kI� ��� � 8 ) Н� �2� � 8 0 8� �O� � 8 7 G�W �� � 8 > �n! �U� � 8 E������� ��� � adspToLpiNocFreqTable �0 $� "$� 5 )3� � 0=�P O� 7M�� j >bkP $� mlToLpiNocFreqTable $� $� "O� 5 )RH � 0 O� 7&�� j >0� $� dal qcom,dal i prm qcom,prm ~ � prm_rsrcs qcom,prm-rsrcs prm-regulator-b1b-e0 qcom,prm-regulator � �B1B_E0 � � � � � @ prm-regulator-l1b-e0 qcom,prm-regulator � �L1B_E0 � � � � � @ prm-regulator-l2b-e0 qcom,prm-regulator � �L2B_E0 � � � � � @ prm-regulator-l5b-e0 qcom,prm-regulator � �L5B_E0 � � � � � @ prm-regulator-l15b-e0 qcom,prm-regulator � �L15B_E0 � � � � � @ prm-regulator-l18b-e0 qcom,prm-regulator � �L18B_E0 � � � � � @ prm-regulator-l1d-e0 qcom,prm-regulator � �L1D_E0 � � � � � @ � prm-regulator-l2d-e0 qcom,prm-regulator � �L2D_E0 � � � � � @ prm-regulator-l3d-e0 qcom,prm-regulator � �L3D_E0 � � � � � @ � prm-regulator-l1f-e0 qcom,prm-regulator � �L1F_E0 � � � � � @ prm-regulator-l7m-e1 qcom,prm-regulator � �L7M_E1 � � � � � @ ! prm-regulator-l3i-e0 qcom,prm-regulator � �L3I_E0 � � � � � @ � prm-regulator-ls1b-e0 qcom,prm-regulator � LS1B_E0 � � � � � @ " prm-regulator-ls2b-e0 qcom,prm-regulator � LS2B_E0 � � � � � @ # prm-regulator-ls3b-e0 qcom,prm-regulator � LS3B_E0 � � � � � @ $ prm-regulator-ls4b-e0 qcom,prm-regulator � LS4B_E0 � � � � � @ % prm-pam
qcom,prm-pam @ & pcie0 pcie0 # @ ' pcie0-ldo1d-e0 2 � $ = � � pcie0-ldo3d-e0 2 � $ = p p pcie0-ldo3i-e0 2 � $ = p p __symbols__ G/soc K/soc/ipcc/ipcc@1103000 V/soc/ipcc/ipcc@11c1000 f/soc/ipcc/ipcc@1281000 v/soc/ipcc/ipcc@1341000 �/soc/ipcc/ipcc@1401000 �/soc/ipcc_legacy@6888004 �/soc/timetick/timer@68a2000 �/soc/timetick/timer@68a3000 �/soc/pinctrl@f100000 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se4_scl * �/soc/pinctrl@f100000/ibi_i3c_qup1_se4_sda * �/soc/pinctrl@f100000/ibi_i3c_qup1_se7_scl * �/soc/pinctrl@f100000/ibi_i3c_qup1_se7_sda *
/soc/pinctrl@f100000/ibi_i3c_qup2_se0_scl * /soc/pinctrl@f100000/ibi_i3c_qup2_se0_sda * 4/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl * I/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda * ^/soc/pinctrl@f100000/ibi_i3c_qup3_se1_scl * s/soc/pinctrl@f100000/ibi_i3c_qup3_se1_sda * �/soc/pinctrl@f100000/ibi_i3c_qup3_se2_scl * �/soc/pinctrl@f100000/ibi_i3c_qup3_se2_sda * �/soc/pinctrl@f100000/ibi_i3c_qup4_se0_scl * �/soc/pinctrl@f100000/ibi_i3c_qup4_se0_sda * �/soc/pinctrl@f100000/ibi_i3c_qup4_se1_scl * �/soc/pinctrl@f100000/ibi_i3c_qup4_se1_sda * /soc/pinctrl@f100000/ibi_i3c_qup4_se2_scl * /soc/pinctrl@f100000/ibi_i3c_qup4_se2_sda ! 0/soc/pinctrl@f100000/qup1_se0_l0 ! </soc/pinctrl@f100000/qup1_se0_l1 ! H/soc/pinctrl@f100000/qup1_se0_l2 ! T/soc/pinctrl@f100000/qup1_se0_l3 ! `/soc/pinctrl@f100000/qup1_se1_l0 ! l/soc/pinctrl@f100000/qup1_se1_l1 ! x/soc/pinctrl@f100000/qup1_se1_l2 ! �/soc/pinctrl@f100000/qup1_se1_l3 ! �/soc/pinctrl@f100000/qup1_se2_l0 ! �/soc/pinctrl@f100000/qup1_se2_l1 ! �/soc/pinctrl@f100000/qup1_se2_l2 ! �/soc/pinctrl@f100000/qup1_se2_l3 ! �/soc/pinctrl@f100000/qup1_se2_l4 ! �/soc/pinctrl@f100000/qup1_se2_l5 ! �/soc/pinctrl@f100000/qup1_se2_l6 ! �/soc/pinctrl@f100000/qup1_se3_l0 ! �/soc/pinctrl@f100000/qup1_se3_l1 ! �/soc/pinctrl@f100000/qup1_se3_l2 ! !/soc/pinctrl@f100000/qup1_se3_l3 ! !/soc/pinctrl@f100000/qup1_se4_l0 ! ! /soc/pinctrl@f100000/qup1_se4_l1 ! !,/soc/pinctrl@f100000/qup1_se4_l2 ! !8/soc/pinctrl@f100000/qup1_se4_l3 ! !D/soc/pinctrl@f100000/qup1_se5_l0 ! !P/soc/pinctrl@f100000/qup1_se5_l1 ! !\/soc/pinctrl@f100000/qup1_se5_l2 ! !h/soc/pinctrl@f100000/qup1_se5_l3 ! !t/soc/pinctrl@f100000/qup1_se6_l0 ! !�/soc/pinctrl@f100000/qup1_se6_l1 ! !�/soc/pinctrl@f100000/qup1_se6_l2 ! !�/soc/pinctrl@f100000/qup1_se6_l3 ! !�/soc/pinctrl@f100000/qup1_se7_l0 ! !�/soc/pinctrl@f100000/qup1_se7_l1 ! !�/soc/pinctrl@f100000/qup1_se7_l2 ! !�/soc/pinctrl@f100000/qup1_se7_l3 ! !�/soc/pinctrl@f100000/qup2_se0_l0 ! !�/soc/pinctrl@f100000/qup2_se0_l1 ! !�/soc/pinctrl@f100000/qup2_se0_l2 ! !�/soc/pinctrl@f100000/qup2_se0_l3 ! "/soc/pinctrl@f100000/qup2_se1_l0 ! "/soc/pinctrl@f100000/qup2_se1_l1 ! " /soc/pinctrl@f100000/qup2_se1_l2 ! "(/soc/pinctrl@f100000/qup2_se1_l3 ! "4/soc/pinctrl@f100000/qup2_se2_l0 ! "@/soc/pinctrl@f100000/qup2_se2_l1 ! "L/soc/pinctrl@f100000/qup2_se2_l2 ! "X/soc/pinctrl@f100000/qup2_se2_l3 ! "d/soc/pinctrl@f100000/qup2_se3_l0 ! "p/soc/pinctrl@f100000/qup2_se3_l1 ! "|/soc/pinctrl@f100000/qup2_se3_l2 ! "�/soc/pinctrl@f100000/qup2_se3_l3 ! "�/soc/pinctrl@f100000/qup2_se4_l0 ! "�/soc/pinctrl@f100000/qup2_se4_l1 ! "�/soc/pinctrl@f100000/qup2_se4_l2 ! "�/soc/pinctrl@f100000/qup2_se4_l3 ! "�/soc/pinctrl@f100000/qup3_se0_l0 ! "�/soc/pinctrl@f100000/qup3_se0_l1 ! "�/soc/pinctrl@f100000/qup3_se0_l2 ! "�/soc/pinctrl@f100000/qup3_se0_l3 ! "�/soc/pinctrl@f100000/qup3_se1_l0 ! # /soc/pinctrl@f100000/qup3_se1_l1 ! # /soc/pinctrl@f100000/qup3_se1_l2 ! #/soc/pinctrl@f100000/qup3_se1_l3 ! #$/soc/pinctrl@f100000/qup3_se1_l4 ! #0/soc/pinctrl@f100000/qup3_se1_l5 ! #</soc/pinctrl@f100000/qup3_se1_l6 ! #H/soc/pinctrl@f100000/qup3_se2_l0 ! #T/soc/pinctrl@f100000/qup3_se2_l1 ! #`/soc/pinctrl@f100000/qup3_se2_l2 ! #l/soc/pinctrl@f100000/qup3_se2_l3 ! #x/soc/pinctrl@f100000/qup3_se3_l0 ! #�/soc/pinctrl@f100000/qup3_se3_l1 ! #�/soc/pinctrl@f100000/qup3_se3_l2 ! #�/soc/pinctrl@f100000/qup3_se3_l3 ! #�/soc/pinctrl@f100000/qup3_se4_l0 ! #�/soc/pinctrl@f100000/qup3_se4_l1 ! #�/soc/pinctrl@f100000/qup3_se4_l2 ! #�/soc/pinctrl@f100000/qup3_se4_l3 ! #�/soc/pinctrl@f100000/qup3_se4_l6 ! #�/soc/pinctrl@f100000/qup3_se5_l0 ! #�/soc/pinctrl@f100000/qup3_se5_l1 ! #�/soc/pinctrl@f100000/qup3_se5_l2 ! $/soc/pinctrl@f100000/qup3_se5_l3 ! $/soc/pinctrl@f100000/qup4_se0_l0 ! $ /soc/pinctrl@f100000/qup4_se0_l1 ! $,/soc/pinctrl@f100000/qup4_se0_l2 ! $8/soc/pinctrl@f100000/qup4_se0_l3 ! $D/soc/pinctrl@f100000/qup4_se1_l0 ! $P/soc/pinctrl@f100000/qup4_se1_l1 ! $\/soc/pinctrl@f100000/qup4_se1_l2 ! $h/soc/pinctrl@f100000/qup4_se1_l3 ! $t/soc/pinctrl@f100000/qup4_se2_l0 ! $�/soc/pinctrl@f100000/qup4_se2_l1 ! $�/soc/pinctrl@f100000/qup4_se2_l2 ! $�/soc/pinctrl@f100000/qup4_se2_l3 ! $�/soc/pinctrl@f100000/qup4_se3_l0 ! $�/soc/pinctrl@f100000/qup4_se3_l1 ! $�/soc/pinctrl@f100000/qup4_se3_l2 ! $�/soc/pinctrl@f100000/qup4_se3_l3 ! $�/soc/pinctrl@f100000/qup4_se4_l0 ! $�/soc/pinctrl@f100000/qup4_se4_l1 ! $�/soc/pinctrl@f100000/qup4_se4_l2 ! $�/soc/pinctrl@f100000/qup4_se4_l3 - %/soc/pinctrl@f100000/top_qup1_se0_i2c_active , % /soc/pinctrl@f100000/top_qup1_se0_i2c_sleep - %3/soc/pinctrl@f100000/top_qup1_se0_spi_active , %K/soc/pinctrl@f100000/top_qup1_se0_spi_sleep . %b/soc/pinctrl@f100000/top_qup1_se0_uart_active - %{/soc/pinctrl@f100000/top_qup1_se0_uart_sleep - %�/soc/pinctrl@f100000/top_qup1_se1_i2c_active , %�/soc/pinctrl@f100000/top_qup1_se1_i2c_sleep - %�/soc/pinctrl@f100000/top_qup1_se1_spi_active , %�/soc/pinctrl@f100000/top_qup1_se1_spi_sleep . %�/soc/pinctrl@f100000/top_qup1_se1_uart_active - &
/soc/pinctrl@f100000/top_qup1_se1_uart_sleep - &"/soc/pinctrl@f100000/top_qup1_se2_i2c_active , &:/soc/pinctrl@f100000/top_qup1_se2_i2c_sleep - &Q/soc/pinctrl@f100000/top_qup1_se2_spi_active , &i/soc/pinctrl@f100000/top_qup1_se2_spi_sleep . &�/soc/pinctrl@f100000/top_qup1_se2_uart_active - &�/soc/pinctrl@f100000/top_qup1_se2_uart_sleep - &�/soc/pinctrl@f100000/top_qup1_se3_i2c_active , &�/soc/pinctrl@f100000/top_qup1_se3_i2c_sleep - &�/soc/pinctrl@f100000/top_qup1_se3_spi_active , &�/soc/pinctrl@f100000/top_qup1_se3_spi_sleep . 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3 /soc/pinctrl@f100000/top_qup4_se1_uart_sleep - 3#/soc/pinctrl@f100000/top_qup4_se2_i2c_active , 3;/soc/pinctrl@f100000/top_qup4_se2_i2c_sleep - 3R/soc/pinctrl@f100000/top_qup4_se2_i3c_active , 3j/soc/pinctrl@f100000/top_qup4_se2_i3c_sleep 1 3�/soc/pinctrl@f100000/top_qup4_se2_i3c_ibi_active 0 3�/soc/pinctrl@f100000/top_qup4_se2_i3c_ibi_sleep - 3�/soc/pinctrl@f100000/top_qup4_se2_spi_active , 3�/soc/pinctrl@f100000/top_qup4_se2_spi_sleep . 3�/soc/pinctrl@f100000/top_qup4_se2_uart_active - 4 /soc/pinctrl@f100000/top_qup4_se2_uart_sleep - 4/soc/pinctrl@f100000/top_qup4_se3_i2c_active , 40/soc/pinctrl@f100000/top_qup4_se3_i2c_sleep - 4G/soc/pinctrl@f100000/top_qup4_se3_spi_active , 4_/soc/pinctrl@f100000/top_qup4_se3_spi_sleep . 4v/soc/pinctrl@f100000/top_qup4_se3_uart_active - 4�/soc/pinctrl@f100000/top_qup4_se3_uart_sleep - 4�/soc/pinctrl@f100000/top_qup4_se4_i2c_active , 4�/soc/pinctrl@f100000/top_qup4_se4_i2c_sleep - 4�/soc/pinctrl@f100000/top_qup4_se4_spi_active , 4�/soc/pinctrl@f100000/top_qup4_se4_spi_sleep . 5/soc/pinctrl@f100000/top_qup4_se4_uart_active - 5 /soc/pinctrl@f100000/top_qup4_se4_uart_sleep 56/soc/pinctrl@7760000 ! 5?/soc/pinctrl@7760000/slimbus_clk " 5K/soc/pinctrl@7760000/slimbus_data . 5X/soc/pinctrl@7760000/slimbus_default_gpio_cfg 5q/soc/pinctrl@75C0000 % 5z/soc/pinctrl@75C0000/ssc_gpio_10_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_11_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_12_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_13_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_14_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_15_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_18_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_19_clk % 5�/soc/pinctrl@75C0000/ssc_gpio_26_clk % 6
/soc/pinctrl@75C0000/ssc_gpio_27_clk % 6/soc/pinctrl@75C0000/ssc_gpio_30_clk % 6*/soc/pinctrl@75C0000/ssc_gpio_31_clk % 6:/soc/pinctrl@75C0000/ssc_gpio_32_clk % 6J/soc/pinctrl@75C0000/ssc_gpio_33_clk % 6Z/soc/pinctrl@75C0000/ssc_gpio_34_clk % 6j/soc/pinctrl@75C0000/ssc_gpio_35_clk $ 6z/soc/pinctrl@75C0000/ssc_gpio_6_clk $ 6�/soc/pinctrl@75C0000/ssc_gpio_7_clk % 6�/soc/pinctrl@75C0000/ssc_qup0_se0_l0 % 6�/soc/pinctrl@75C0000/ssc_qup0_se0_l1 % 6�/soc/pinctrl@75C0000/ssc_qup0_se1_l0 % 6�/soc/pinctrl@75C0000/ssc_qup0_se1_l1 % 6�/soc/pinctrl@75C0000/ssc_qup0_se2_l0 % 6�/soc/pinctrl@75C0000/ssc_qup0_se2_l1 % 6�/soc/pinctrl@75C0000/ssc_qup0_se2_l2 % 7/soc/pinctrl@75C0000/ssc_qup0_se2_l3 % 7/soc/pinctrl@75C0000/ssc_qup0_se2_l4 % 7(/soc/pinctrl@75C0000/ssc_qup0_se2_l5 % 78/soc/pinctrl@75C0000/ssc_qup0_se3_l0 % 7H/soc/pinctrl@75C0000/ssc_qup0_se3_l1 % 7X/soc/pinctrl@75C0000/ssc_qup0_se4_l0 % 7h/soc/pinctrl@75C0000/ssc_qup0_se4_l1 % 7x/soc/pinctrl@75C0000/ssc_qup0_se4_l2 % 7�/soc/pinctrl@75C0000/ssc_qup0_se4_l3 % 7�/soc/pinctrl@75C0000/ssc_qup0_se4_l4 % 7�/soc/pinctrl@75C0000/ssc_qup0_se4_l5 % 7�/soc/pinctrl@75C0000/ssc_qup0_se5_l0 % 7�/soc/pinctrl@75C0000/ssc_qup0_se5_l1 % 7�/soc/pinctrl@75C0000/ssc_qup0_se5_l2 % 7�/soc/pinctrl@75C0000/ssc_qup0_se5_l3 % 7�/soc/pinctrl@75C0000/ssc_qup0_se6_l0 % 8/soc/pinctrl@75C0000/ssc_qup0_se6_l1 % 8/soc/pinctrl@75C0000/ssc_qup0_se6_l2 % 8(/soc/pinctrl@75C0000/ssc_qup0_se6_l3 % 88/soc/pinctrl@75C0000/ssc_qup0_se7_l0 % 8H/soc/pinctrl@75C0000/ssc_qup0_se7_l1 % 8X/soc/pinctrl@75C0000/ssc_qup0_se7_l2 % 8h/soc/pinctrl@75C0000/ssc_qup0_se7_l3 % 8x/soc/pinctrl@75C0000/ssc_qup1_se0_l0 % 8�/soc/pinctrl@75C0000/ssc_qup1_se0_l1 % 8�/soc/pinctrl@75C0000/ssc_qup1_se1_l0 % 8�/soc/pinctrl@75C0000/ssc_qup1_se1_l1 % 8�/soc/pinctrl@75C0000/ssc_qup1_se2_l0 % 8�/soc/pinctrl@75C0000/ssc_qup1_se2_l1 % 8�/soc/pinctrl@75C0000/ssc_qup1_se2_l2 % 8�/soc/pinctrl@75C0000/ssc_qup1_se2_l3 % 8�/soc/pinctrl@75C0000/ssc_qup1_se3_l0 % 9/soc/pinctrl@75C0000/ssc_qup1_se3_l1 % 9/soc/pinctrl@75C0000/ssc_qup1_se4_l0 % 9(/soc/pinctrl@75C0000/ssc_qup1_se4_l1 % 98/soc/pinctrl@75C0000/ssc_qup1_se5_l0 % 9H/soc/pinctrl@75C0000/ssc_qup1_se5_l1 % 9X/soc/pinctrl@75C0000/ssc_qup1_se5_l2 % 9h/soc/pinctrl@75C0000/ssc_qup1_se5_l3 % 9x/soc/pinctrl@75C0000/ssc_qup1_se6_l0 % 9�/soc/pinctrl@75C0000/ssc_qup1_se6_l1 % 9�/soc/pinctrl@75C0000/ssc_qup1_se6_l2 % 9�/soc/pinctrl@75C0000/ssc_qup1_se6_l3 - 9�/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_active , 9�/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_sleep - 9�/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_active , 9�/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_sleep 1 :/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_active 0 :2/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_sleep - :M/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_active , :e/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_sleep - :|/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_active , :�/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_sleep 1 :�/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_active 0 :�/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_sleep - :�/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_active , :�/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_sleep - ;/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_active , ;)/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_sleep 1 ;@/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_active 0 ;\/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_sleep - ;w/soc/pinctrl@75C0000/qup_ssc0_se2_spi_active , ;�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_sleep / ;�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_3w_sleep 0 ;�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_3w_active - ;�/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_active , ;�/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_sleep - <
/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_active , <"/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_sleep 1 <9/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_active 0 <U/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_sleep - <p/soc/pinctrl@75C0000/qup_ssc0_se4_i2c_active , <�/soc/pinctrl@75C0000/qup_ssc0_se4_i2c_sleep - <�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_active , <�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_sleep 0 <�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_3w_active / <�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_3w_sleep - =/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_active , =/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_sleep - =2/soc/pinctrl@75C0000/qup_ssc0_se5_spi_active , =J/soc/pinctrl@75C0000/qup_ssc0_se5_spi_sleep 0 =a/soc/pinctrl@75C0000/qup_ssc0_se5_spi_3w_active / =|/soc/pinctrl@75C0000/qup_ssc0_se5_spi_3w_sleep . =�/soc/pinctrl@75C0000/qup_ssc0_se5_uart_active - =�/soc/pinctrl@75C0000/qup_ssc0_se5_uart_sleep - =�/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_active , =�/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_sleep - =�/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_active , >/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_sleep 1 >%/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_active 0 >A/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_sleep . >\/soc/pinctrl@75C0000/qup_ssc0_se6_uart_active - >u/soc/pinctrl@75C0000/qup_ssc0_se6_uart_sleep - >�/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_active , >�/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_sleep . >�/soc/pinctrl@75C0000/qup_ssc0_se7_uart_active - >�/soc/pinctrl@75C0000/qup_ssc0_se7_uart_sleep - >�/soc/pinctrl@75C0000/qup_ssc1_se0_i2c_active , ?/soc/pinctrl@75C0000/qup_ssc1_se0_i2c_sleep - ? /soc/pinctrl@75C0000/qup_ssc1_se0_i3c_active , ?4/soc/pinctrl@75C0000/qup_ssc1_se0_i3c_sleep 1 ?K/soc/pinctrl@75C0000/qup_ssc1_se0_i3c_ibi_active 0 ?g/soc/pinctrl@75C0000/qup_ssc1_se0_i3c_ibi_sleep - ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i2c_active , ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i2c_sleep - ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i3c_active , ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i3c_sleep 1 ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i3c_ibi_active 0 ?�/soc/pinctrl@75C0000/qup_ssc1_se1_i3c_ibi_sleep - @/soc/pinctrl@75C0000/qup_ssc1_se2_i2c_active , @//soc/pinctrl@75C0000/qup_ssc1_se2_i2c_sleep - @F/soc/pinctrl@75C0000/qup_ssc1_se2_i3c_active , @^/soc/pinctrl@75C0000/qup_ssc1_se2_i3c_sleep 1 @u/soc/pinctrl@75C0000/qup_ssc1_se2_i3c_ibi_active 0 @�/soc/pinctrl@75C0000/qup_ssc1_se2_i3c_ibi_sleep - @�/soc/pinctrl@75C0000/qup_ssc1_se2_spi_active , @�/soc/pinctrl@75C0000/qup_ssc1_se2_spi_sleep 0 @�/soc/pinctrl@75C0000/qup_ssc1_se2_spi_3w_active / @�/soc/pinctrl@75C0000/qup_ssc1_se2_spi_3w_sleep - A/soc/pinctrl@75C0000/qup_ssc1_se3_i2c_active , A(/soc/pinctrl@75C0000/qup_ssc1_se3_i2c_sleep - A?/soc/pinctrl@75C0000/qup_ssc1_se3_i3c_active , AW/soc/pinctrl@75C0000/qup_ssc1_se3_i3c_sleep 1 An/soc/pinctrl@75C0000/qup_ssc1_se3_i3c_ibi_active 0 A�/soc/pinctrl@75C0000/qup_ssc1_se3_i3c_ibi_sleep - A�/soc/pinctrl@75C0000/qup_ssc1_se4_i2c_active , A�/soc/pinctrl@75C0000/qup_ssc1_se4_i2c_sleep - A�/soc/pinctrl@75C0000/qup_ssc1_se5_i2c_active , A�/soc/pinctrl@75C0000/qup_ssc1_se5_i2c_sleep - B/soc/pinctrl@75C0000/qup_ssc1_se5_spi_active , B/soc/pinctrl@75C0000/qup_ssc1_se5_spi_sleep 0 B2/soc/pinctrl@75C0000/qup_ssc1_se5_spi_3w_active / BM/soc/pinctrl@75C0000/qup_ssc1_se5_spi_3w_sleep - Bg/soc/pinctrl@75C0000/qup_ssc1_se6_i2c_active , B/soc/pinctrl@75C0000/qup_ssc1_se6_i2c_sleep - B�/soc/pinctrl@75C0000/qup_ssc1_se6_i3c_active , B�/soc/pinctrl@75C0000/qup_ssc1_se6_i3c_sleep 1 B�/soc/pinctrl@75C0000/qup_ssc1_se6_i3c_ibi_active 0 B�/soc/pinctrl@75C0000/qup_ssc1_se6_i3c_ibi_sleep . B�/soc/pinctrl@75C0000/qup_ssc1_se6_uart_active - C/soc/pinctrl@75C0000/qup_ssc1_se6_uart_sleep
C-/soc/vdd_mxa
C5/soc/vdd_mxc C=/soc/vdd_cx CD/soc/vdd_lpi_mx CO/soc/vdd_lpi_cx CZ/soc/clock-controller@100000 C^/soc/clock-controller@1f40000 Ck/soc/clock-controller@7700000 C{/soc/clock-controller@6bc0000 C�/soc/clock-controller@7b00000 C�/soc/clock-controller@6e40000 C�/soc/clock-controller@7880000 C�/soc/cesta@7213000 " C�/soc/qdss/tpath_lpass_lpi_dl_tpda + C�/soc/qdss/tpath_lpass_lpi_audio_hm_dl_tpda C�/soc/qdss/tpath_lpi_stm C�/soc/qdss/tpath_lpi_etm D /soc/qdss/tpath_sdc_etm D/soc/qdss/tpath_stm D$/soc/qdss/tpath_sdc_itm D2/soc/qdss/tpath_lpass_lpi_noc DF/soc/qdss/tpath_lpi_aon_noc DX/soc/qdss/tpath_aoc Db/soc/qdss/tpath_enpu0_noc Dr/soc/qdss/tpath_enpu1_noc D�/soc/funnel@10041000 D�/soc/funnel@11353000 D�/soc/funnel@11304000 D�/soc/funnel@11344000 h/soc/tnoc@11331000 C�/soc/tpda@11352000 C�/soc/tpda@11347000 D�/soc/systemcache@31800000 D�/soc/ssc_ibi_cd_domains E /soc/ibi_ssc_0_cfg@7500000 E/soc/ibi_ssc_1_cfg@7510000 E(/soc/ibi_ssc_2_cfg@7520000 E6/soc/ibi_ssc_3_cfg@7530000 ED/soc/ibi_ssc_4_cfg@7540000 ER/soc/ibi_ssc_5_cfg@7550000 E`/soc/ibi_ssc_6_cfg@7560000 En/soc/ibi_ssc_7_cfg@7570000 E|/soc/ibi_ssc_8_cfg@7580000 E�/soc/ibi_ssc_9_cfg@7590000 E�/soc/ibi_top_0_cfg@EC90000 E�/soc/ibi_top_1_cfg@ECA0000 E�/soc/ibi_top_2_cfg@ECB0000 E�/soc/ibi_top_3_cfg@ECC0000 E�/soc/ibi_top_4_cfg@ECD0000 E�/soc/ibi_top_5_cfg@ECE0000 E�/soc/ibi_top_6_cfg@ECF0000 E�/soc/ibi_top_7_cfg@ED00000 F/soc/ibi_top_8_cfg@ED10000 F/soc/spmi-bus@c400000 F /soc/spmi-bus@c400000/pmic@0 6 F)/soc/spmi-bus@c400000/pmic@0/spmi-vadc@92/therm_table F5/soc/spmi-bus@c436000 9 F?/soc/kernel_test_devices@0/interrupt-controller@10140000 FD/sw ' FG/sw/prm/prm_rsrcs/prm-regulator-b1b-e0 ' FN/sw/prm/prm_rsrcs/prm-regulator-l1b-e0 ' FU/sw/prm/prm_rsrcs/prm-regulator-l2b-e0 ' F\/sw/prm/prm_rsrcs/prm-regulator-l5b-e0 ( Fc/sw/prm/prm_rsrcs/prm-regulator-l15b-e0 ( Fk/sw/prm/prm_rsrcs/prm-regulator-l18b-e0 ' Fs/sw/prm/prm_rsrcs/prm-regulator-l1d-e0 ' Fz/sw/prm/prm_rsrcs/prm-regulator-l2d-e0 ' F�/sw/prm/prm_rsrcs/prm-regulator-l3d-e0 ' F�/sw/prm/prm_rsrcs/prm-regulator-l1f-e0 ' F�/sw/prm/prm_rsrcs/prm-regulator-l7m-e1 ' F�/sw/prm/prm_rsrcs/prm-regulator-l3i-e0 ( F�/sw/prm/prm_rsrcs/prm-regulator-ls1b-e0 ( F�/sw/prm/prm_rsrcs/prm-regulator-ls2b-e0 ( F�/sw/prm/prm_rsrcs/prm-regulator-ls3b-e0 ( F�/sw/prm/prm_rsrcs/prm-regulator-ls4b-e0 F�/sw/prm/prm-pam F�/sw/prm/prm-pam/pcie0 model compatible #address-cells #size-cells proc-name chip-info phandle supported-hosts host remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents tx-channel rx-channel host-id fflags max-entries dest proc irq core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets reg client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping offset out-mask timer-name timer-freq timer-num timer-interrupt ngpios width qcom,strongpull egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name mux config qcom,slewrate qcom,sleep-config regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id reg-names #clock-cells base_port num_ports atid sync_period tpdm_name tpda tpda_port dataset cmb_size cti_channels cti_triggers dbg_regs pwrdbg_ctrl_reg lpi_funnel lpi_funnel_port port_ddrss_lpi_ddrss_lpi_trace_noc tpath cti_name tnoc_id tnoc_funnel_name tstype tpda_name port_occupied_mask value llcc-common-reg llcc-lcp-reg partial-cache lpi-base scid num_ssc_qup ibi_base protocol se_island_config tre_list_size ibi_se_index se_mode load_fw dfs_mode clock-names clocks ibi_id gpii gpii_irq mgr_irq status qup_id qup_common_offset se_wrapper_base_offset core_frequency qup_flags num_se sdc_gpii_list core_offset ibi_instance se_flags FIFO_MODE protocol_supported interface_supported num_gpiis ring_size_multiplier core_irq pdc_irq parent_wakeup_gpio shared_se od_frequency i2c_hs_i3c_src_freq is_pipeline_enable log_level pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 i2c_hub num_top_qups irq_num qup0_cfg qup1_cfg qup2_cfg qup3_cfg qup4_cfg uStructVer pszInstName uaMasterEA pszHwioBase uHwioBaseOffset uHwioBase hBamDev uIntId uBamIntId uMyEE smbus_clk smbus_data uGpioIntNum uaNumEndPoints uaVoltageVote bIsLpiTlmm LA uaEA uDataLineMask num_device_props tlmm_name_str svs_npa_str is_master default_clock_gear prog_bam_trust island_vote subsystem_sleep_vote tlmm_offset tlmm_val svs_npa use_gpio_int no_retention num_local_ports local_port_base local_channel_base shared_channel_base num_local_counters is_lpm_used_for_mgr_bam_trans lpm_mgr_sb_region_base lpm_mgr_sb_region_size is_lpm_sat_sb_region_dump_enable lpm_sat_sb_region_base lpm_sat_sb_region_size ee_assign rev MmpmCoreIdType MmpmCoreInstanceIdType pClientName pwrCtrlFlag callBackFlag MMPM_Callback cbFcnStackSize gsi_pa tcsr_addr tcsr_gpii_offset tcsr_irq gpii_interrupts num_gpii active use-interrupt sid mid pmic bid therm-tbl label hw-ch hw-settle avg-sp dec-ratio cal-method scaling scale-fcn pull-up asid int-table arr_id hw-common-params adctm-hw-params trip-range interrupt-controller #interrupt-cells message test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt PD_indicator test_oem_entry service_id instance_id qdss_service_id pram_name pram_size pt_name wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id ssctl_srv sys_m_smem_ssr_res wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id client_name client_id llccs scid-mapping-reg clients dump-pools diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks clientNum routes hw_instance masterIcbPort slaveIcbPort min index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 GlbCtxtHWMutexNumber qcom,prm-query qcom,prm-publish-rsrcs qcom,prm-rsrc-alias qcom,prm-vreg qcom,prm-control qcom,prm-type qcom,pm-index qcom,pm-sid qcom,pm-bid qcom,prm-clock pam-name pam-mode-count pam-supply pam-modes soc ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy SystemTimer WakeUpTimer tlmm ibi_i3c_qup1_se4_scl ibi_i3c_qup1_se4_sda ibi_i3c_qup1_se7_scl ibi_i3c_qup1_se7_sda ibi_i3c_qup2_se0_scl ibi_i3c_qup2_se0_sda ibi_i3c_qup2_se1_scl ibi_i3c_qup2_se1_sda ibi_i3c_qup3_se1_scl ibi_i3c_qup3_se1_sda ibi_i3c_qup3_se2_scl ibi_i3c_qup3_se2_sda ibi_i3c_qup4_se0_scl ibi_i3c_qup4_se0_sda ibi_i3c_qup4_se1_scl ibi_i3c_qup4_se1_sda ibi_i3c_qup4_se2_scl ibi_i3c_qup4_se2_sda qup1_se0_l0 qup1_se0_l1 qup1_se0_l2 qup1_se0_l3 qup1_se1_l0 qup1_se1_l1 qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se2_l4 qup1_se2_l5 qup1_se2_l6 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 qup1_se4_l1 qup1_se4_l2 qup1_se4_l3 qup1_se5_l0 qup1_se5_l1 qup1_se5_l2 qup1_se5_l3 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup1_se7_l0 qup1_se7_l1 qup1_se7_l2 qup1_se7_l3 qup2_se0_l0 qup2_se0_l1 qup2_se0_l2 qup2_se0_l3 qup2_se1_l0 qup2_se1_l1 qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 qup2_se2_l1 qup2_se2_l2 qup2_se2_l3 qup2_se3_l0 qup2_se3_l1 qup2_se3_l2 qup2_se3_l3 qup2_se4_l0 qup2_se4_l1 qup2_se4_l2 qup2_se4_l3 qup3_se0_l0 qup3_se0_l1 qup3_se0_l2 qup3_se0_l3 qup3_se1_l0 qup3_se1_l1 qup3_se1_l2 qup3_se1_l3 qup3_se1_l4 qup3_se1_l5 qup3_se1_l6 qup3_se2_l0 qup3_se2_l1 qup3_se2_l2 qup3_se2_l3 qup3_se3_l0 qup3_se3_l1 qup3_se3_l2 qup3_se3_l3 qup3_se4_l0 qup3_se4_l1 qup3_se4_l2 qup3_se4_l3 qup3_se4_l6 qup3_se5_l0 qup3_se5_l1 qup3_se5_l2 qup3_se5_l3 qup4_se0_l0 qup4_se0_l1 qup4_se0_l2 qup4_se0_l3 qup4_se1_l0 qup4_se1_l1 qup4_se1_l2 qup4_se1_l3 qup4_se2_l0 qup4_se2_l1 qup4_se2_l2 qup4_se2_l3 qup4_se3_l0 qup4_se3_l1 qup4_se3_l2 qup4_se3_l3 qup4_se4_l0 qup4_se4_l1 qup4_se4_l2 qup4_se4_l3 top_qup1_se0_i2c_active top_qup1_se0_i2c_sleep top_qup1_se0_spi_active top_qup1_se0_spi_sleep top_qup1_se0_uart_active top_qup1_se0_uart_sleep top_qup1_se1_i2c_active top_qup1_se1_i2c_sleep top_qup1_se1_spi_active top_qup1_se1_spi_sleep top_qup1_se1_uart_active top_qup1_se1_uart_sleep top_qup1_se2_i2c_active top_qup1_se2_i2c_sleep top_qup1_se2_spi_active top_qup1_se2_spi_sleep top_qup1_se2_uart_active top_qup1_se2_uart_sleep top_qup1_se3_i2c_active top_qup1_se3_i2c_sleep top_qup1_se3_spi_active top_qup1_se3_spi_sleep top_qup1_se3_uart_active top_qup1_se3_uart_sleep top_qup1_se4_i2c_active top_qup1_se4_i2c_sleep top_qup1_se4_i3c_active top_qup1_se4_i3c_sleep top_qup1_se4_i3c_ibi_active top_qup1_se4_i3c_ibi_sleep top_qup1_se4_spi_active top_qup1_se4_spi_sleep top_qup1_se4_uart_active top_qup1_se4_uart_sleep top_qup1_se5_i2c_active top_qup1_se5_i2c_sleep top_qup1_se5_spi_active top_qup1_se5_spi_sleep top_qup1_se5_uart_active top_qup1_se5_uart_sleep top_qup1_se6_i2c_active top_qup1_se6_i2c_sleep top_qup1_se6_spi_active top_qup1_se6_spi_sleep top_qup1_se6_uart_active top_qup1_se6_uart_sleep top_qup1_se7_i2c_active top_qup1_se7_i2c_sleep top_qup1_se7_i3c_active top_qup1_se7_i3c_sleep top_qup1_se7_i3c_ibi_active top_qup1_se7_i3c_ibi_sleep top_qup1_se7_spi_active top_qup1_se7_spi_sleep top_qup1_se7_uart_active top_qup1_se7_uart_sleep top_qup2_se0_i2c_active top_qup2_se0_i2c_sleep top_qup2_se0_i3c_active top_qup2_se0_i3c_sleep top_qup2_se0_i3c_ibi_active top_qup2_se0_i3c_ibi_sleep top_qup2_se0_spi_active top_qup2_se0_spi_sleep top_qup2_se0_uart_active top_qup2_se0_uart_sleep top_qup2_se1_i2c_active top_qup2_se1_i2c_sleep top_qup2_se1_i3c_active top_qup2_se1_i3c_sleep top_qup2_se1_i3c_ibi_active top_qup2_se1_i3c_ibi_sleep top_qup2_se1_spi_active top_qup2_se1_spi_sleep top_qup2_se1_uart_active top_qup2_se1_uart_sleep top_qup2_se2_i2c_active top_qup2_se2_i2c_sleep top_qup2_se2_spi_active top_qup2_se2_spi_sleep top_qup2_se2_uart_active top_qup2_se2_uart_sleep top_qup2_se3_i2c_active top_qup2_se3_i2c_sleep top_qup2_se3_spi_active top_qup2_se3_spi_sleep top_qup2_se3_uart_active top_qup2_se3_uart_sleep top_qup2_se4_i2c_active top_qup2_se4_i2c_sleep top_qup2_se4_spi_active top_qup2_se4_spi_sleep top_qup2_se4_uart_active top_qup2_se4_uart_sleep top_qup3_se0_i2c_active top_qup3_se0_i2c_sleep top_qup3_se0_spi_active top_qup3_se0_spi_sleep top_qup3_se0_uart_active top_qup3_se0_uart_sleep top_qup3_se1_i2c_active top_qup3_se1_i2c_sleep top_qup3_se1_spi_active top_qup3_se1_spi_sleep top_qup3_se1_uart_active top_qup3_se1_uart_sleep top_qup3_se2_i2c_active top_qup3_se2_i2c_sleep top_qup3_se2_spi_active top_qup3_se2_spi_sleep top_qup3_se2_uart_active top_qup3_se2_uart_sleep top_qup3_se3_i2c_active top_qup3_se3_i2c_sleep top_qup3_se3_spi_active top_qup3_se3_spi_sleep top_qup3_se3_uart_active top_qup3_se3_uart_sleep top_qup3_se4_i2c_active top_qup3_se4_i2c_sleep top_qup3_se4_spi_active top_qup3_se4_spi_sleep top_qup3_se4_uart_active top_qup3_se4_uart_sleep top_qup3_se5_i2c_active top_qup3_se5_i2c_sleep top_qup3_se5_spi_active top_qup3_se5_spi_sleep top_qup3_se5_uart_active top_qup3_se5_uart_sleep top_qup4_se0_i2c_active top_qup4_se0_i2c_sleep top_qup4_se0_i3c_active top_qup4_se0_i3c_sleep top_qup4_se0_i3c_ibi_active top_qup4_se0_i3c_ibi_sleep top_qup4_se0_spi_active top_qup4_se0_spi_sleep top_qup4_se0_uart_active top_qup4_se0_uart_sleep top_qup4_se1_i2c_active top_qup4_se1_i2c_sleep top_qup4_se1_i3c_active top_qup4_se1_i3c_sleep top_qup4_se1_i3c_ibi_active top_qup4_se1_i3c_ibi_sleep top_qup4_se1_spi_active top_qup4_se1_spi_sleep top_qup4_se1_uart_active top_qup4_se1_uart_sleep top_qup4_se2_i2c_active top_qup4_se2_i2c_sleep top_qup4_se2_i3c_active top_qup4_se2_i3c_sleep top_qup4_se2_i3c_ibi_active top_qup4_se2_i3c_ibi_sleep top_qup4_se2_spi_active top_qup4_se2_spi_sleep top_qup4_se2_uart_active top_qup4_se2_uart_sleep top_qup4_se3_i2c_active top_qup4_se3_i2c_sleep top_qup4_se3_spi_active top_qup4_se3_spi_sleep top_qup4_se3_uart_active top_qup4_se3_uart_sleep top_qup4_se4_i2c_active top_qup4_se4_i2c_sleep top_qup4_se4_spi_active top_qup4_se4_spi_sleep top_qup4_se4_uart_active top_qup4_se4_uart_sleep lpi_tlmm slimbus_clk slimbus_data slimbus_default_gpio_cfg ssc_tlmm ssc_gpio_10_clk ssc_gpio_11_clk ssc_gpio_12_clk ssc_gpio_13_clk ssc_gpio_14_clk ssc_gpio_15_clk ssc_gpio_18_clk ssc_gpio_19_clk ssc_gpio_26_clk ssc_gpio_27_clk ssc_gpio_30_clk ssc_gpio_31_clk ssc_gpio_32_clk ssc_gpio_33_clk ssc_gpio_34_clk ssc_gpio_35_clk ssc_gpio_6_clk ssc_gpio_7_clk ssc_qup0_se0_l0 ssc_qup0_se0_l1 ssc_qup0_se1_l0 ssc_qup0_se1_l1 ssc_qup0_se2_l0 ssc_qup0_se2_l1 ssc_qup0_se2_l2 ssc_qup0_se2_l3 ssc_qup0_se2_l4 ssc_qup0_se2_l5 ssc_qup0_se3_l0 ssc_qup0_se3_l1 ssc_qup0_se4_l0 ssc_qup0_se4_l1 ssc_qup0_se4_l2 ssc_qup0_se4_l3 ssc_qup0_se4_l4 ssc_qup0_se4_l5 ssc_qup0_se5_l0 ssc_qup0_se5_l1 ssc_qup0_se5_l2 ssc_qup0_se5_l3 ssc_qup0_se6_l0 ssc_qup0_se6_l1 ssc_qup0_se6_l2 ssc_qup0_se6_l3 ssc_qup0_se7_l0 ssc_qup0_se7_l1 ssc_qup0_se7_l2 ssc_qup0_se7_l3 ssc_qup1_se0_l0 ssc_qup1_se0_l1 ssc_qup1_se1_l0 ssc_qup1_se1_l1 ssc_qup1_se2_l0 ssc_qup1_se2_l1 ssc_qup1_se2_l2 ssc_qup1_se2_l3 ssc_qup1_se3_l0 ssc_qup1_se3_l1 ssc_qup1_se4_l0 ssc_qup1_se4_l1 ssc_qup1_se5_l0 ssc_qup1_se5_l1 ssc_qup1_se5_l2 ssc_qup1_se5_l3 ssc_qup1_se6_l0 ssc_qup1_se6_l1 ssc_qup1_se6_l2 ssc_qup1_se6_l3 qup_ssc0_se0_i2c_active qup_ssc0_se0_i2c_sleep qup_ssc0_se0_i3c_active qup_ssc0_se0_i3c_sleep qup_ssc0_se0_i3c_ibi_active qup_ssc0_se0_i3c_ibi_sleep qup_ssc0_se1_i2c_active qup_ssc0_se1_i2c_sleep qup_ssc0_se1_i3c_active qup_ssc0_se1_i3c_sleep qup_ssc0_se1_i3c_ibi_active qup_ssc0_se1_i3c_ibi_sleep qup_ssc0_se2_i2c_active qup_ssc0_se2_i2c_sleep qup_ssc0_se2_i3c_active qup_ssc0_se2_i3c_sleep qup_ssc0_se2_i3c_ibi_active qup_ssc0_se2_i3c_ibi_sleep qup_ssc0_se2_spi_active qup_ssc0_se2_spi_sleep qup_ssc0_se2_spi_3w_sleep qup_ssc0_se2_spi_3w_active qup_ssc0_se3_i2c_active qup_ssc0_se3_i2c_sleep qup_ssc0_se3_i3c_active qup_ssc0_se3_i3c_sleep qup_ssc0_se3_i3c_ibi_active qup_ssc0_se3_i3c_ibi_sleep qup_ssc0_se4_i2c_active qup_ssc0_se4_i2c_sleep qup_ssc0_se4_spi_active qup_ssc0_se4_spi_sleep qup_ssc0_se4_spi_3w_active qup_ssc0_se4_spi_3w_sleep qup_ssc0_se5_i2c_active qup_ssc0_se5_i2c_sleep qup_ssc0_se5_spi_active qup_ssc0_se5_spi_sleep qup_ssc0_se5_spi_3w_active qup_ssc0_se5_spi_3w_sleep qup_ssc0_se5_uart_active qup_ssc0_se5_uart_sleep qup_ssc0_se6_i2c_active qup_ssc0_se6_i2c_sleep qup_ssc0_se6_i3c_active qup_ssc0_se6_i3c_sleep qup_ssc0_se6_i3c_ibi_active qup_ssc0_se6_i3c_ibi_sleep qup_ssc0_se6_uart_active qup_ssc0_se6_uart_sleep qup_ssc0_se7_i2c_active qup_ssc0_se7_i2c_sleep qup_ssc0_se7_uart_active qup_ssc0_se7_uart_sleep qup_ssc1_se0_i2c_active qup_ssc1_se0_i2c_sleep qup_ssc1_se0_i3c_active qup_ssc1_se0_i3c_sleep qup_ssc1_se0_i3c_ibi_active qup_ssc1_se0_i3c_ibi_sleep qup_ssc1_se1_i2c_active qup_ssc1_se1_i2c_sleep qup_ssc1_se1_i3c_active qup_ssc1_se1_i3c_sleep qup_ssc1_se1_i3c_ibi_active qup_ssc1_se1_i3c_ibi_sleep qup_ssc1_se2_i2c_active qup_ssc1_se2_i2c_sleep qup_ssc1_se2_i3c_active qup_ssc1_se2_i3c_sleep qup_ssc1_se2_i3c_ibi_active qup_ssc1_se2_i3c_ibi_sleep qup_ssc1_se2_spi_active qup_ssc1_se2_spi_sleep qup_ssc1_se2_spi_3w_active qup_ssc1_se2_spi_3w_sleep qup_ssc1_se3_i2c_active qup_ssc1_se3_i2c_sleep qup_ssc1_se3_i3c_active qup_ssc1_se3_i3c_sleep qup_ssc1_se3_i3c_ibi_active qup_ssc1_se3_i3c_ibi_sleep qup_ssc1_se4_i2c_active qup_ssc1_se4_i2c_sleep qup_ssc1_se5_i2c_active qup_ssc1_se5_i2c_sleep qup_ssc1_se5_spi_active qup_ssc1_se5_spi_sleep qup_ssc1_se5_spi_3w_active qup_ssc1_se5_spi_3w_sleep qup_ssc1_se6_i2c_active qup_ssc1_se6_i2c_sleep qup_ssc1_se6_i3c_active qup_ssc1_se6_i3c_sleep qup_ssc1_se6_i3c_ibi_active qup_ssc1_se6_i3c_ibi_sleep qup_ssc1_se6_uart_active qup_ssc1_se6_uart_sleep vdd_mxa vdd_mxc vdd_cx vdd_lpi_mx vdd_lpi_cx gcc lpass_aon_cc lpass_aon_mx_cc lpass_audio_cc lpass_core_cc lpass_lpmla_cc scc lpass_cesta tpath_lpass_lpi_dl_tpda tpath_lpass_lpi_audio_hm_dl_tpda tpath_lpi_stm tpath_lpi_etm tpath_sdc_etm tpath_stm tpath_sdc_itm tpath_lpass_lpi_noc tpath_lpi_aon_noc tpath_aoc tpath_enpu0_noc tpath_enpu1_noc in_fun0_in_fun0_cxatbfunnel lpass_lpi_fun1_fun1_cxatbfunnel aoss_apb_fun0 lpass_lpi_fun0_fun0_cxatbfunnel systemcache0 ssc_ibi_cd_domains ibi_ssc_0_cfg ibi_ssc_1_cfg ibi_ssc_2_cfg ibi_ssc_3_cfg ibi_ssc_4_cfg ibi_ssc_5_cfg ibi_ssc_6_cfg ibi_ssc_7_cfg ibi_ssc_8_cfg ibi_ssc_9_cfg ibi_top_0_cfg ibi_top_1_cfg ibi_top_2_cfg ibi_top_3_cfg ibi_top_4_cfg ibi_top_5_cfg ibi_top_6_cfg ibi_top_7_cfg ibi_top_8_cfg spmi_bus pmk8850_0 therm_table spmi_bus1 intc sw B1B_E0 L1B_E0 L2B_E0 L5B_E0 L15B_E0 L18B_E0 L1D_E0 L2D_E0 L3D_E0 L1F_E0 L7M_E1 L3I_E0 LS1B_E0 LS2B_E0 LS3B_E0 LS4B_E0 pam pcie0 �
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�� � 8 � ( � � qcom,kaanapali qcom,kaanapali board-id ,qsh_process-kaanapali-1.0-adsp 6 � soc @ cxstmtrace@16000000 qcom,stmtrace H L @ V @ lpistmtrace@7100000 qcom,stmtrace H L @ V @ sw @ core cpt_boot_test PD_Access_control ` X OEM_Flavor_Validation m mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config | � " debugtrace qcom,debugtrace � products sdcloader qcom,sdcloader sdc_params � < � � � � � � �a� sdc_physpool � *'P ? power qdsp_pm pd qcom,pd-qsh-process T debugtools tms_diag qcom,tms_diag h � eic qcom,eic q � � Z version_tbl qcom,image_version_tbl_idx � services tuna dynamic_heap qcom,dynamic_heap client_id_config client_id_00 �DYNAMIC_MEM_CLIENT_ID_SENSOR � client_id_01 �DYNAMIC_MEM_CLIENT_ID_TEST � diag qcom,sensor_user_diagcfg diagcfg_cmd � h � j � = 1 L e ~' diagcfg_param � � � � � � � 4 2 H � ^ { � � � � � � 0 NQSH_ISLAND_POOL _QSH_ISLAND_POOL qup_user_pd_feature qcom,sw-qup-user-pd-controller u __symbols__ �/soc �/sw model compatible #address-cells #size-cells proc-name chip-info phandle reg base_port num_ports PD_indicator test_oem_entry service_id instance_id qdss_service_id wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size QDI_QDSP_PM_USER_ID image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx client_name client_id diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool user_pd_island_enabled soc sw �
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